Negative voltage level conversion circuit for flash memories

Abstract

The invention discloses a negative voltage level conversion circuit for flash memories, which belongs to the field of integrated circuit designs. The connection relation of the negative voltage level conversion circuit is as follows: VIN input voltage is connected with the common node between an INV1 inverter and a first bootstrap circuit, the INV1 inverter is also connected with a second bootstrap circuit, a first voltage conversion circuit is respectively connected with the first bootstrap circuit, the second bootstrap circuit and a second voltage conversion circuit, and the second voltage conversion circuit is also connected with VOUT output voltage. The negative voltage level conversion circuit has the advantages that: the structure is simple, the level conversion speed is high, power consumption is little, the driving capability is strong, and the application range is wide; and the negative voltage level conversion circuit can normally operate when the voltage of a power supply is decreased, enhances the function of isolating the voltage of the power supply, decreases the capability of two cross-coupled NMOS (N-channel metal oxide semiconductor) transistors in pulling down the voltage, and reduces the competition between a selection circuit and a cross-coupled circuit during input signal inversion.

Description

Technical field [0001] The invention belongs to the field of integrated circuit design, and particularly relates to a negative voltage level conversion circuit for flash memory. Background technique [0002] At present, flash memory is widely used in portable devices such as mobile phones, cameras, and palmtop computers. It has the advantages of not losing data when power-off, high programming speed, and high integration. figure 1 It is a cross-sectional view of a conventional flash memory cell, which uses a stacked gate structure composed of a polysilicon control gate 10 and a floating gate 12. On the p-type substrate 16, a source region 14 and a drain region 15 of n+ structure are formed by implantation. In addition, the floating gate 12 and the substrate 16 are separated by an insulating layer 13, and the control gate 10 and the floating gate 12 are separated by an insulating layer 11. This stacked gate structure makes the threshold voltage of the memory cell seen from the co...

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Problems solved by technology

[0008] In the existing negative level conversion circuit, as the power supply voltage drops, the level conversion delay and conversion power consumption increase significantly, and at the same time the size of the transistor is difficult to reduce, which increases the layout area and increases the process cost

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