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Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing

A semiconductor and device technology, applied in the field of wiring pattern formation, can solve problems such as circuit short circuit

Inactive Publication Date: 2005-10-26
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Copper polishing residues may cause short circuits in lines

Method used

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  • Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing
  • Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing
  • Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] figure 1 is a cross-sectional view showing a semiconductor substrate circuit device manufactured by a wiring pattern forming method according to a first embodiment of the present invention. A semiconductor substrate 1 made of p-type silicon has an element separation insulating film 2 formed on a surface layer of the substrate. The element isolation insulating film 2 defines an active region. A MOS transistor 3 is formed in the active region. The MOS transistor 3 has a gate insulating film 3a, a gate electrode 3b, and impurity diffusion regions 3c and 3d. One of the impurity diffusion regions 3c and 3d is a source region, and the other is a drain region.

[0027] The impurity diffusion regions 3a and 3d formed in the surface layer on both sides of the gate electrode 3b have a lightly doped drain (LDD) structure. The gate 3b has insulating sidewall spacers 3e formed on the sidewalls of the gate 3b. The side wall liner 3e is used as a mask when ion implantation is per...

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PUM

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Abstract

A first insulating film is formed on an underlying substrate, the first insulating film being made of a first insulating material. A second insulating film is formed on the first insulating film, the second insulating film being made of a second insulating material different from the first insulating material. A trench is formed through the second and first insulating film, the trench reaching at least an intermediate depth of the first insulating film. A wiring layer made of a conductive material is deposited on the second insulating film, the wiring layer burying the trench. The wiring layer is polished to leave the wiring layer in the trench. The wiring layer and second insulating film are polished until the first insulating film is exposed. Irregularity such as dishing and erosion can be suppressed from being formed.

Description

[0001] Cross References to Related Applications [0002] This application is based on Japanese Patent Application No. 2002-166621 filed on June 7, 2002, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a wiring pattern forming method, in particular to a method of forming a trench through an insulating layer, depositing a conductive material on the insulating layer to bury the trench with the conductive material, and polishing the conductive material to form a groove in the trench. A wiring patterning method that leaves a portion of conductive material. Background technique [0004] A damascene method with high speed and reliability is used in a wiring pattern forming method of a high-density semiconductor integrated circuit device. The dual damascene method is a basic method for manufacturing complex semiconductor integrated circuit devices, which forms trenches and via holes for wiring patterns thr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/3205B24B7/20B24B37/04H01L21/302H01L21/304H01L21/3105H01L21/311H01L21/321H01L21/4763H01L21/768
CPCH01L21/3212H01L21/76808H01L21/7684H01L21/31053H01L21/28
Inventor 宫嶋基守柄沢章孝细田勉大塚敏志
Owner FUJITSU SEMICON LTD