Ultra low jitter clock generation device and method for storage device and radio frequency system

Abstract

A clock generation device includes a delay-locked loop and plurality of programmable counters. The plurality of programmable counters are coupled to delay-locked loop. Each of the programmable counters has a separate output. The delay-locked loop is configured to generate a plurality of phase delay line outputs. A hard drive includes the delay-locked loop and the programmable counters, which generate multiple timing signals such as read, write, servo, and system timing signals. The method of generating a plurality of timing pulses through the programmable counters.

Description

technical field [0001] This case relates to a clock generation system, especially a device and method for reducing signal jitter and generating clock signals. Background technique [0002] Generally speaking, when using the read, write and servo channels in a hard disk system, three different clock sources may be required. The read head and the write head require separate clock signals to convert an electrical signal to a magnetic signal and a magnetic signal to an electrical signal, respectively. Different clock signals are also required for the servo action to correctly position the magnetic head on the surface of the hard disk. In each of the above systems, the required timing pulses are very high-frequency time pulses. [0003] Timing management for the read, write, and servo channels can be handled by a multiple timing synthesizer with a programmable output frequency over a wide frequency band. However, some multi-timing synthesis devices have an operational consider...

AI Technical Summary

Problems solved by technology

This phase error may degrade the operational performance of some timing synthesis components

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