Method for multi-phase division with frequency-doubled phase interpolation and correlative circuit
A multi-phase, phase interpolator technology, applied in the direction of electrical pulse generator circuits, logic circuits to generate pulses, phase shifters, etc., can solve the overall circuit burden of increasing power requirements, difficult to meet short clock cycles, shortened clock cycles, etc. question
Inactive Publication Date: 2006-06-21
VIA TECH INC
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Problems solved by technology
Under the trend of modern high operating clock, the cycle of the clock will be shortened accordingly; therefore, it is difficult for the ring oscillator realized by multi-stage inverter to meet the requirement of short clock cycle
If the clock period must be shortened, the ring oscillator must use higher power to drive each inverter to quickly convert the signal level in order to reduce the delay time Tg, but this will increase the power demand and the burden on the overall circuit
Method used
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[0028] Please refer to Figure 5 . Figure 5 It is a schematic diagram of the functional blocks of the multiple phase generation circuit 20 of the present invention. The multi-phase generating circuit 20 is used to generate multiple output clocks with the same frequency and different phases to achieve phase division, and can be applied to precise timing control and time-to-digital converters. The multi-phase generating circuit 20 is provided with a clock generator 24 , a slicer 26 , and a phase interpolator 28 . When the multi-phase generation circuit 20 wants to generate multiple output clocks with the same frequency and different phases at a certain frequency, the clock generator 24 will be used to generate reference clocks with the same frequency and different phases, and the frequencies of these reference clocks are all times the output clock Frequency of. These reference clocks will be trimmed by the limiter 26, and the trimmed reference clocks will be input into the p...
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The invention provides a multi-phase division method and related circuits. The method comprises the steps of: when generating M output clocks with the same frequency as f and different phases, generating N reference clocks with the same frequency as (M / N)*f and different phases (M>N), and then Different cycles of each reference clock start to trigger (N / M) frequency division, so that each reference clock generates (M / N) output clocks with different phases, and finally M different phases are generated from N reference clocks. phase of the output clock.
Description
technical field [0001] The invention relates to a phase division method and a related circuit, in particular to a method and a related circuit for completing phase division by performing phase interpolation with a frequency-multiplied multi-phase reference clock. Background technique [0002] In the modern information society, all kinds of electronic devices used to process and store data information also need to process electronic data at a faster speed, higher density and accumulation degree. The precision of operation will also increase accordingly. For example, in an optical disc recorder, since data must be accurately recorded on an optical disc with a very high data storage density, the timing control of the data writing operation of the optical drive must also be precisely controlled. When the optical drive uses its read head to send and receive laser light to the optical disc for data access, although the optical drive can analyze a clock from the laser reflected ba...
Claims
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IPC IPC(8): H03K3/26H03B27/00G11B20/10H03K3/03H03K5/00H03K5/08H03K5/13H03K5/15H03K23/68H03L7/099H03L7/18
CPCH03K3/0322H03K5/08H03K5/133H03K5/1506H03K23/68H03K2005/00286H03L7/0998H03L7/18
Inventor 林有铨
Owner VIA TECH INC