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Patterning method for integrated circuit

An integrated circuit, patterning technology, applied in the patterning field that can reduce the limitations of the lithography etching process

Inactive Publication Date: 2006-02-15
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Another object of the present invention is to provide a patterning method applied to integrated circuits to solve the various shortcomings that occur when using a hard mask layer to overcome photolithography and etching processes.

Method used

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  • Patterning method for integrated circuit
  • Patterning method for integrated circuit
  • Patterning method for integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0024] Figure 1A to Figure 1D As shown, it is a schematic flowchart of a method for patterning an integrated circuit according to a preferred embodiment of the present invention.

[0025] Please refer to Figure 1A Firstly, a material layer 102 is formed on a substrate 100 . Wherein, the material layer 102 may be a dielectric material layer (such as an oxide layer, a silicon nitride layer or a silicon oxynitride layer) or a conductive material layer (such as a metal layer or a polysilicon layer). And, a patterned photoresist layer 104 is formed on the material layer 102, wherein the thickness of the photoresist layer 104 is thin enough to overcome a photolithography process when patterning the photoresist layer. limit, while increasing the resolution of the photolithography process. Moreover, the size of the photoresist layer 104 is a target critical dimension.

[0026] After that, please refer to Figure 1B , form a cover layer 106 on the surface of the photoresist layer...

no. 2 example

[0032] Figure 2A to Figure 2CAs shown, it is a schematic flowchart of a method for patterning an integrated circuit according to another preferred embodiment of the present invention.

[0033] Please refer to Figure 2A Firstly, a material layer 102 is formed on a substrate 200 . Wherein, the material layer 202 may be a dielectric material layer (such as an oxide layer, a silicon nitride layer or a silicon oxynitride layer) or a conductive material layer (such as a metal layer or a polysilicon layer). And, a patterned photoresist layer 204 is formed on the material layer 202, wherein the thickness of the photoresist layer 204 is thin enough to overcome the limitations of a photolithography process when patterning the photoresist layer. limit, and the formed photoresist layer 204 has a dimension "c" smaller than the target critical dimension.

[0034] After that, please refer to Figure 2B , a capping layer 206 is formed on the surface of the photoresist layer 204, wherein...

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Abstract

A pattern method for IC includes such steps as generating a material layer on substrate, generating a pattern photoresist layer with a thickness thin enough, generating a lining layer, treating the lining layer to remove the lining layer on side surface of photoresist layer, and etching for patterning the material layer.

Description

technical field [0001] The present invention relates to a patterning method applied to integrated circuits, and in particular to a patterning method capable of reducing the limitations of photolithography and etching processes. Background technique [0002] As the size of semiconductor devices shrinks day by day, the requirements for the resolution of the photolithography process are also getting higher and higher. Since the resolution of the photolithography process is mainly determined by the wavelength of the exposure light source (Wavelength), there must be a certain distance between the mask pattern (Mask Pattern) obtained by the photolithography (or etching) process. When the mask layer is an etching mask layer, it means that the size of the gap or the opening of the layer pattern to be etched defined by it cannot be further reduced. [0003] The limit of the photolithography process currently used to pattern the photoresist layer is approximately the ability to patte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027G03F7/00
Inventor 钟维民
Owner MACRONIX INT CO LTD