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Selective output edge ratio control

A rate and output signal technology, applied in the field of integrated circuits with controlled output edge slew rate, can solve problems such as limitation, slew rate control cannot be programmed, and occupied die.

Inactive Publication Date: 2006-03-22
FAIRCHILD SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This unique design is limited because the technology uses many components and thus takes up a large portion of the die
US Patent 5,489,862 by the same inventor discloses a feedback slew rate control circuit, but the slew rate control cannot be programmed
[0006] U.S. Patent No. 5,537,070 discloses a slew rate control circuit using a reference voltage and a current source, but only controls the high-to-low output transition of an open-drain circuit

Method used

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  • Selective output edge ratio control
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Examples

Experimental program
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Embodiment Construction

[0021] figure 1 is a simplified schematic block diagram of one embodiment of the invention. The IN signal is a logic signal from active low to active high. Here, ground and Vcc are used, but practically any other logic level voltage can be used. Inverter 2 is shown as a single pole double switch S1 switching at the threshold of inverter 2 .

[0022] exist figure 1 Among them, when the IN signal is at low level, the switch S1 is driven to position A. As shown in the figure, the current source 4 drives the gate 6 of the output transistor 8 to be at a high level, thereby turning on the transistor 8 and driving OUT to be at a low level. When the IN signal is at a high level, the switch is at position B, and the current source 10 drives the gate to a low level, so that the transistor 8 is turned off, and thus R1 pulls OUT to a high level.

[0023] Considering the rest of the circuit design the current source 4, including the equivalent capacitance of the gate 6, to drive the ga...

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Abstract

A circuit using current starved pull up and pull down transistors is arranged to connect a current source via each transistors to an output transistor stage. The current source values are selected so that the starved transistors provide a known voltage edge rate profile as a function of the current sources and the parameters of the transistors. Two or more additional current sources, that when enabled contribute current in parallel with the first current sources such that controlled edge rate profiles are selectively speeded up in response the enabled current sources. An enable input is provided for each additional current source for selectably controlling the faster or slower edge rate profiles. Reference voltages are used to determine the current source values along with transistor parameters. Preferably the transistor are MOSFETs.

Description

technical field [0001] This application relates to integrated circuits, and more particularly to integrated circuits with controlled output edge slew rates. Background technique [0002] Higher data speeds and / or power and temperature requirements have worked to reduce logic voltage swings and dictate the slew rates of output signals. The 5.0 and 3.3 volt logic levels are giving way to logic swings of a few hundred or tens of millivolts. [0003] These requirements manifest themselves, especially in buffers and drivers, and often in open-drain structures that are pulled up externally to whatever practical voltage the designer may choose for compatibility. As is well known in the art, the "or" function can also be directly realized by connecting the open drains together. [0004] Another limitation of high-logic-level circuits is self-generated noise and increased power consumption when driving signals with high-speed changes at higher speeds. For example, when many buffer...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0175H03K3/00H03K5/12H03K17/16
CPCH03K17/164
Inventor C·克莱恩M·J·米斯克
Owner FAIRCHILD SEMICON CORP