Semiconductor memory device with control for auxiliary word lines for memory cell selection

Abstract

A semiconductor memory device has a main row decoder for controlling a main word line, an auxiliary row decoder for controlling auxiliary word lines, and auxiliary word line drive circuits controllable by the main word line and the auxiliary word selecting lines, for controlling auxiliary word lines to select memory cells. The semiconductor memory device incorporates a hierarchical word line system where word lines do not need to be lined with metallized interconnections. The main word line and the auxiliary word selecting lines control the auxiliary word line drive circuits to supply an arbitrary negative voltage generated by a negative potential generator to an auxiliary word line in an unselected state, and to keep only a selected auxiliary word line at a high level in a selected state.

Description

technical field [0001] The present invention relates to a semiconductor storage device, in particular to a semiconductor storage device with an auxiliary word line drive circuit, wherein the auxiliary word line drive circuit is used to control the main word line by a main decoder circuit and auxiliary word select lines controlled by an auxiliary decoder circuit activate auxiliary word lines for memory cell selection. Background technique [0002] In recent years, due to the improvement of semiconductor microfabrication technology, in order to obtain a larger storage capacity, semiconductor memory devices have been highly integrated at an increasing rate. Among semiconductor memory devices, a dynamic random access memory (DRAM) capable of storing and retaining data can be easily highly integrated to obtain a larger storage capacity because a memory cell consists of two elements, a transistor and a capacitor . DRAMs with a storage capacity of gigabits have been mentioned in ...

AI Technical Summary

Problems solved by technology

However, as the size of semiconductor memory devices decreases, it becomes difficult to connect word lines with metallization interconnects to reduce interconnect induction in the word line pitch.

This defect also exists in the first conventional semiconductor memory device, and hinders the reduction in size and increase in storage capacity of semiconductor memory devices

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