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Synchronized write data on high speed memory bus

A technology for writing data and storage devices, applied in the field of synchronous memory systems, and can solve problems such as impossible to write clock cycles

Inactive Publication Date: 2006-12-20
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the phase shift is caused by devices external to the synchronous semiconductor memory device, it is impossible for the synchronous semiconductor memory device to accurately determine the appropriate write clock cycle WCLK to start receiving write data

Method used

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  • Synchronized write data on high speed memory bus
  • Synchronized write data on high speed memory bus
  • Synchronized write data on high speed memory bus

Examples

Experimental program
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Embodiment Construction

[0023] Referring now to the drawings, in which like reference numerals denote like elements, Figure 3 shows a figure 2 A more detailed diagram of a synchronous semiconductor memory device of device 202 . In an exemplary embodiment, the synchronous semiconductor memory device is a double data rate SDRAM with independent command and write clocks. A double data rate SDRAM is an SDRAM that receives write data on both the rising and falling edges of the write clock. Each rising or falling edge of the write clock cycle is called a signal point. The synchronous semiconductor memory device contains many circuits for control, addressing, and input / output of data. For example, the synchronous semiconductor memory device includes control logic 601 that receives a command clock CCLK on signal line 104 , a write clock WCLK on signal line 103 , and commands and addresses CMD / ADDR on a number of signal lines 105 . The control logic 601 includes a command decoder 602 for decoding received...

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Abstract

Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.

Description

technical field [0001] The present invention relates generally to synchronous memory systems, and more particularly to synchronous writing of data on a high speed memory bus. Background technique [0002] FIG. 1 illustrates an exemplary computer system 1 . The computer system 1 includes a processor 401 , a memory system 2 and an expansion bus controller 402 . Memory system 2 and expansion bus controller 402 are coupled to processor 401 via local bus 400 . The expansion bus controller 402 is also coupled to one or more expansion buses 403 to which various peripheral devices can be attached, such as mass storage devices, keyboards, mice, graphics adapters, and media adapters. [0003] The memory system 2 includes a memory controller 100 connected by a memory bus 106 to a number of memory modules 200 . The memory bus includes a number of signal lines 101-105 that communicate with data DATA (on number of lines 101), data strobe STROBE, write clock WCLK, command clock CCLK, an...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10G06F13/28G11C7/22G11C11/407G06F12/00G06F13/16G11C11/4076
CPCG11C7/1084G11C7/22G11C11/4078G11C8/20G11C7/1078G11C16/22G11C7/24G11C11/4076G11C7/1072G11C11/40
Inventor B·基斯B·约翰森
Owner MICRON TECH INC