Buffering method of SDH class logical simulation excitation data

A technology for logic simulation and excitation data, applied in the field of communication or electronics, it can solve the problems of slow SDH logic simulation speed, inconvenient parameter configuration and modification, etc., to achieve the effect of improving efficiency, improving automation and fast access.

Inactive Publication Date: 2007-02-14
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0005] The invention provides a SDH logic simulation incentive data caching method, which solves the problems of slow speed of SDH logic simulation and inconvenient parameter configuration and modification

Method used

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  • Buffering method of SDH class logical simulation excitation data
  • Buffering method of SDH class logical simulation excitation data

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Embodiment Construction

[0021] The technical solution provided by the present invention is different from the prior art solution in that: one is to consider all the modules produced by the SDH logic simulation excitation as a whole, and each module is no longer independent of each other, but is related before and after; The second is to use a FIFO (First Input First Output) device (the storage medium can be the memory of the computer) to replace the files in the original technical solution (the storage medium is the hard disk of the computer), which can greatly speed up the access of the incentive generation program to the intermediate data Speed, and all configured parameters are stored in the memory, and the value of the parameters involved in each module can be dynamically accessed by designing a corresponding graphical interface.

[0022] The work process that the SDH class logic simulation stimulus data of the present invention produces is as follows figure 2 As shown, the description is as fol...

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Abstract

This invention relates to a method for buffering SDH kind logic emulation excitation data including: A, a message generation module generates an initial message to be put into a FIFO device, B, a LAPS package module takes a certain volume of message from the FIFO device to package and put them into a second FIFO device, C, a VC4 virtual cascade image module gets the packaged message from the second FIFO device to carry out VC4 image to generate STM-1 frame to be put in a third FIFO device, D, a bus interface conversion module gets STM-1 frame data from a third FIFO device for the bus interface conversion to generate bus data to be put in a fourth FIFO device to be transmitted to a tested device.

Description

technical field [0001] The invention relates to simulation technology in the field of communication or electronics, in particular to an SDH logic simulation excitation data caching method. Background technique [0002] In the SDH (Synchronous Digital Hierarchy, synchronous digital system) logic simulation, excitation generation is a complicated task, because SDH involves many protocols, the processing process is complicated, and a large amount of temporary data will be generated in the middle. How to manage and Working with these temporary data has always been a pain point for simulators. [0003] At present, in SDH logic simulation, the method of stimulus generation is to design each module required in the process of stimulus generation into an independent program (in C / C++, it is embodied as a main function named main), The temporary data generated by each independent program will be written into a file, and then the next related independent program will obtain the requir...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/455H04L12/56H04L29/06H04L12/861
Inventor 程智辉李伟东潘武飞
Owner HUAWEI TECH CO LTD
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