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Pulse Signal transforming delay regulating circuit

A signal and circuit technology, which is applied in the field of delay circuits for adjusting pulse signal delays, can solve problems affecting waveforms and device performance, and achieve the effects of eliminating delays, easy design, and eliminating coupling noise

Inactive Publication Date: 2003-01-01
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] One problem with circuit 100 is that the feedback scheme allows noise to couple into the circuit
This affects the waveform which in turn affects the performance of the whole unit

Method used

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  • Pulse Signal transforming delay regulating circuit
  • Pulse Signal transforming delay regulating circuit
  • Pulse Signal transforming delay regulating circuit

Examples

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Embodiment Construction

[0029] As described above, the present invention provides delay circuits. The present invention will now be described in detail.

[0030] Referring now to FIG. 2, a circuit 200 is constructed in accordance with a general embodiment of the present invention. Circuit 200 includes an input node 204 for receiving an input signal VIN. Circuit 200 also includes a floating node 206, and optionally an output node 208 on which an output voltage VO is developed.

[0031] Buffer 210 is coupled between input node 204 and floating node 206 . The buffer is preferably constituted by an inverter.

[0032] The circuit 200 additionally includes a detector 220 . Detector 220 outputs voltage VO on output node 208 . If the voltage VFN of the floating node 206 is lower than the threshold voltage VLT, the output voltage VO has a first level, such as a high level. Otherwise, the output voltage VO has a second level, such as a low level. The high level can be a voltage source level, such as VDD...

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PUM

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Abstract

A delay circuit has an input node receiveing an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.

Description

technical field [0001] The invention relates to the field of integrated circuits, and more particularly, to a delay circuit for adjusting the delay of pulse signals. Background technique [0002] In integrated circuits, delay circuits are required to provide signal delay for various functions. Delay circuits can be found in the internal clock generators of the clock signals in dynamic random access memory (DRAM), as well as in the power supplies of internal semiconductor chips used to control the timing of pump voltages. [0003] Referring now to FIG. 1 , an example of such a delay circuit 100 is shown. Circuit 100 was originally disclosed in US Patent No. 5,920,221. [0004] The voltage is input at node 10 which is connected to an RC network 11 . The RC network 11 comprises: a resistor 12; and two oppositely coupled directional capacitors 18,19. The signal passes through a signal detector 14 and an inverter circuit 16 . The voltage output on node 17 is fed back to capa...

Claims

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Application Information

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IPC IPC(8): H03H11/26H03K5/00H03K5/08H03K5/13
CPCH03K5/08H03K2005/00071H03K5/13H03H11/265
Inventor 金圭现郑大铉
Owner SAMSUNG ELECTRONICS CO LTD