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Storage circuit with test compression function

A storage circuit and circuit technology, applied in the field of storage circuits, can solve the problem of reducing the recovery rate of waste elements, etc.

Inactive Publication Date: 2003-06-04
SOCIONEXT INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, when the compression rate during the test is increased, the possible problem is that the recovery rate of defective cells decreases

Method used

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  • Storage circuit with test compression function
  • Storage circuit with test compression function
  • Storage circuit with test compression function

Examples

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no. 1 example

[0033] FIG. 2 is a configuration diagram of an output circuit of the first embodiment, image 3 is a timing chart of the test mode of the first embodiment. As an example, this embodiment is a 4-bit output structure. In the test mode, 2 bits are compressed and tested at the same time, and two sets of compressed outputs are serially output from the first input / output terminal DQ1.

[0034] As shown in FIG. 2, 4-bit output data is output from 4-bit common data buses cdb1 to cdb4 at the element array 10 constituting the memory core. The 4-bit data on the common data bus is latched in the figure 1shown in the sense amplifier RA. In addition, the common data bus is shared by many memory cores, and the 4-bit output of the selected memory core is output to the common data bus.

[0035] The 4-bit common data buses cdb1 to cdb4 are connected to the 4 output control circuits 24, respectively. Also, the four output control circuits 24 are connected to the four input / output terminals D...

no. 2 example

[0052] FIG. 8 is a configuration diagram of an output circuit of the second embodiment, and Figure 9 is an operation timing chart of this embodiment. For the second preferred embodiment, in response to a test command sent from the outside, the test control circuit 30 sets the test control signal tes1z to a high level. The result is to enter test mode. The high byte signal / UB then directly controls the selection of the two compression test outputs. In other words, if the high byte signal / UB is low, the first test mode is entered, and the compressed output signals of the common data buses cdb1 and cdb2 are output to the output terminal DQ1. If the high byte signal / UB is high, the second test mode is entered, and the compressed output signals of the common data buses cdb3 and cdb4 are output to the output terminal DQ1. For this selection method of the compression test output signal, in the test mode, as long as the external signal is not used as a read command, any externa...

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Abstract

A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=LxM) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.

Description

technical field [0001] The present invention relates to a memory circuit with test compression function, more specifically, to this kind of memory circuit: it can increase the recovery rate of waste elements while reducing the test compression rate, and can also increase the synchronous test rate of test equipment. Background technique [0002] Recently, there is a tendency to increase the capacity of semiconductor memories related to devices such as portable information terminals due to factors such as storing image data. As a result, the test times for these memory circuits of increased capacity have become longer and longer, and a demand for memory circuits with shorter test times has arisen. [0003] When testing mass storage circuits, simultaneous measurements are made on many memory chips connected in parallel with the test equipment. In order to simultaneously test more memory chips, even regardless of the limit of the number of probes built into the test equipment, ...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R31/3185G11C29/00G11C29/14G11C29/34G11C29/38G11C29/40
CPCG11C29/40G11C29/00
Inventor 藤冈伸也藤枝和一郎原浩太
Owner SOCIONEXT INC
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