Method for combination of self alignment contact procedure with self aligned silicon compound procedure

Abstract

This invention discloses a method combining the self-aligned contact process and the self-aligned silicide process. The method comprises the following steps: providing a semiconductor substrate the surface of which defines an internal memory area and a border area with the internal memory area and the border area containing respectively a plurality of doped gate and source / drain electrodes areas first; then removing the gate electrode using etching by a predetermined gate level; next performing a self-aligned metal silicide process to form a metal silicide on the surfaces of the gate electrodes and the source / drain areas in the border; then forming a covering layer for the gate electrodes on the metal silicide on the surface of the gate electrodes and covering at least one interlayer dielectric layer on the semiconductor substrate.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a method combining a self-aligned contact process and a self-aligned silicide process. Background technique [0002] In the manufacturing process of integrated circuit components, the self-aligned contact (self-aligned contact, SAC) process is widely used to define and shorten the distance between adjacent gates to achieve the purpose of reducing the chip size, especially in memory products ( Such as: ditch DRAM, stack DRAM, FLASH memory) production. The self-aligned silicide (salicide) process is widely used in the logic (Logic) process. The method is to deposit a metal layer on the silicon layer and heat-treat the metal layer to make the silicon react with the metal to form a metal silicide. It can be applied in On the surface of the gate or source / drain to achieve the effect of reducing the resistance value. Such as figure 1 As shown, the gate structure of a general m...

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Problems solved by technology

[0006] However, the above-mentioned method only applies the metal silicide process to the surface of the gate structure 28 and the source / drain region 30 in the logic circuit area 5, and cannot simultaneously form the metal silicide on the surface of the polysilicon layer 16 in the memory area 7.

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