Multiplier and shift device using signed digit representation

Abstract

The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and / or finite impulse response filters FIR filters as well as programmable and / or adaptive digital filters. As the multiplier is represented in CSD coding, the number of necessary shifting operations can be reduced and the number of necessary additions can be reduced, thus contributing to a reduced area needed for a hardware realization of a shifting means and a multiplier device on a silicon chip.

Description

technical field [0001] The present invention relates to multipliers and shifters. Background technique [0002] With the expansion of digital signal processing, multipliers suitable for multiplying digital signals are required. [0003] Generally, when multiplying two digital signals each representing a digital value, the multiplication is performed as follows. Assume that A represents the multiplicand and B represents the multiplier, and also assume (for example only) that A and B are each represented by 4 bits (usually represented by n bits) (bits are also called digits). [0004] In order to multiply A=11 by B=7 (in decimal notation) (this gives 77 in decimal notation), if A, B are binary signals, the following must be implemented. [0005] For each bit of the multiplier, the value of the multiplicand will be shifted by the number of bits corresponding to the weight of the bits of the multiplier. That is, for the least significant bit (representing 2 0 ), a zero shift...

AI Technical Summary

Problems solved by technology

[0080] Thus, such a structure is quite bulky and will occupy a large amount of silicon area, which is undesirable in view of the purpose of miniaturizing IC chip designs

In addition, the cost of such devices increases with the increase in chip area occupied

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