Semiconductor device

Abstract

A semiconductor device with laser-programmable fuses for repairing a memory defect found after production, in which guard rings and fuse patterns are designed to take up less chip space. The semiconductor device has a fuse pattern running parallel to the longitudinal axis of a rectangular guard ring, and patterns branching from the fuse pattern and drawn out of the guard ring in the direction perpendicular to that axis. The semiconductor device also has a plurality of memory cell arrays, each coupled to an I/O port for receiving and sending memory signals. One of those arrays is reserved as a redundant memory cell array for repair purposes. The device further has switch circuits for switching the connection between the I/O ports and memory cell arrays, selecting either default memory cell arrays of the I/O ports or their adjacent memory cell arrays, including the redundant memory cell array.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a fuse for repairing defects found after manufacture. Background technique [0002] A semiconductor device including memory circuits has a redundant memory array for repairing memory defects found after manufacture. The repair process disconnects the defective memory cell array from other circuits by blowing laser programmable fuses provided in the device, and restores its functionality with the now activated redundant array. In this chip structure, the fuse patterns are respectively disposed under rectangular guard rings, so that the laser beams irradiated inside the guard rings will irradiate the desired fuse patterns. 6(A) and (B) illustrate guard ring and fuse patterns formed in one semiconductor device. Specifically, FIG. 6(A) is a plan view, and FIG. 6(B) is a cross-sectional view taken along line 100-100 in FIG. 6(A). [0003] As s...

AI Technical Summary

Problems solved by technology

However, the fuse pattern structure of Figure 7(A) takes up a lot of chip space because each fuse requires space for one window and retainer

Although the structure of Fig. 7(B) is more efficient than Fig. 7(A) in terms of fuse and retainer area, the conductors connecting each fuse patte...

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