Method for making semiconductor device

Abstract

A lower barrier layer made of tantalum nitride (19) having a thickness of approximately 25nm is deposited by sputtering on an insulating film (17) inclusive of the sidewall surfaces and the bottom surfaces of a via hole (17a) and an upper-interconnect-forming groove (18a). The sputtering is performed under the conditions where approximately 10kW of DC source power is applied to a target. Thereafter, the DC source power is reduced to approximately 2kW, and approximately 200W of RF power is applied to a semiconductor substrate. Here, the lower barrier layer is subjected to a sputter-etching process employing argon gas at an etching amount of approximately 5nm, so that a part of the lower barrier layer deposited on the bottom surface of the via hole is at least partially deposited on the lower part of the sidewall surface of the via hole.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device having metal wiring, and more particularly to a method of manufacturing a semiconductor device having metal wiring formed by a dual damascene method. Background technique [0002] In recent years, due to the high integration of semiconductor devices, the wiring has been increasingly miniaturized and multilayered. [0003] Next, a method for forming a multilayered metal wiring in a conventional semiconductor device will be described with reference to the drawings. [0004] Figure 7(a) ~ Figure 7(c) 8( a ) and FIG. 8( b ) are cross-sectional structures of the part containing the through hole in the multilayer wiring shown according to the process sequence of the conventional semiconductor device manufacturing method. [0005] As shown in FIG. 7(a), a first insulating film 101 and a second insulating film 102 made of silicon oxide or the like are sequentially deposited on ...

AI Technical Summary

Problems solved by technology

[0012] If it cannot be ensured that the upper wiring formation layer 112A is indeed filled in the through hole 107a, the following phenomenon will occur, that is, the resistance of the channel (via) 112C and the wiring 105, 112B increases, and electron migration or stress migration occurs. The reliability of multilayer wiring is greatly reduced

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