Low-power consumption related bi-sampling circuit structure

A technology of correlated double sampling and circuit structure, applied in the field of microelectronics, can solve the problems of many transistors, increased power consumption, low power consumption design without optimized readout circuit, etc.

Inactive Publication Date: 2004-03-31
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] At present, the readout circuit of the pixel is basically designed using the classic correlated double sampling circuit, which uses many transistors, which invisibly increases power consumption; and does not optimize the low-power design of the readout circuit

Method used

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  • Low-power consumption related bi-sampling circuit structure

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Embodiment Construction

[0012] refer to figure 1 as shown, figure 1 It is the structure diagram of the first embodiment of the low power consumption correlated double sampling circuit structure of the present invention. The present invention is a low power consumption correlated double sampling circuit structure, which has the advantages of low power consumption and simple circuit structure, including:

[0013] Two P-type MOS tubes 2 and 3 for switching, the drains of P-type MOS tubes 2 and 3 for switching are connected to the signal input terminal 1, the gate of P-type MOS tube 2 for switching is connected to the set switch signal 12, and the P-type MOS tubes for switching are connected to the signal input terminal 1. The gate of the N-type MOS tube 3 is connected to the sampling switch signal 13; the capacitor uses N-type MOS tubes 4 and 5, and the drains and sources of the N-type MOS tubes 4 and 5 are grounded for the capacitor, and the N-type MOS tube 4 is used for the capacitor. The gate is con...

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Abstract

The invention is a low-consumption correlative double-sampling circuit structure, including: two sampling-switch P-type MOS tubes, the sources linked with signal input end, and the grids with set andsampling switch signals, respectively; two capacitance N-type MOS tubes, the grids linked with the drains of the two switch tubes, respectively; a reset switch N-type MOS tube, the grid linked with reset signal, the drain with that of one switch tube, and the source with the drain of the other one; a differential amplifying pair tube, the grids linked with the two switch tubes, respectively, a N-type MOS tubeí»s source with signal input end, and the other oneí»s source with equivalent current source, and the drains with signal output end; two-time sampling signals are stored in the capacitance N-type MOS tubes, and the pair tubes outputs useful signals to finish the sampling course.

Description

technical field [0001] The invention belongs to the design of low-power integrated circuits in the field of microelectronics, and is a novel correlation double sampling circuit. Background technique [0002] A key technology for detecting weak signals is to suppress noise to improve the signal-to-noise ratio of the output signal. The design of the pixel readout circuit is a key part of the CMOS image sensor design. Try to suppress or weaken the noise in the readout circuit, which can reduce the requirements for designing subsequent image processing circuits. The CMOS readout circuit is mainly composed of MOS transistors and MOS capacitors. Therefore, the noise of the readout circuit is composed of the inherent noise of electronic devices and the additional noise introduced by the circuit structure. The additional noise introduced by the circuit structure can be suppressed or weakened by a reasonable circuit design. . Fixed pattern noise is one of the main noises of CMOS im...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H01L21/82H01L27/00
Inventor金湘亮陈杰仇玉林
OwnerINST OF MICROELECTRONICS CHINESE ACAD OF SCI