Dual loop PLL

Abstract

In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up / down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a 1 / 2 of a previous addition / subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a 1 / 2 of the previous addition / subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up / down counter 8 increments or decrements by a 1 / 2 value of the previous addition / subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

Description

technical field [0001] The present invention relates to a dual loop PLL having a frequency comparison loop and a phase comparison loop. Background technique [0002] Conventionally, as a PLL (Phase Locked Loop), there is a dual-loop PLL that has a frequency comparison loop and a phase comparison loop, and obtains phase synchronization in a wide frequency range without increasing the gain of a voltage-controlled oscillator. Regarding this prior art, it is described, for example, in the following document, which is Yi-Cheng Chang, Edwin W. Greeneich, "MONOLITHIC PHASE-LOCKED LOOP CIRCUITS WITH COARSE-STEERING ACQUISITIONAID (COARSE-STEERING ACQUISITIONAID) Monolithic PLL)" Circuit and Systems, 1999.42nd Midwest Symposium on, Volume: l, 1999 Page(s): 283-286 vol.1. [0003] Since the gain of the voltage-controlled oscillator can be reduced even if the broadband localization is realized, the dual-loop PLL has the advantage of reducing the influence of fluctuations in the input ...

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Problems solved by technology

[0011] However, in the above-mentioned conventional dual-loop PLL, since the up-down counter 8 in the frequency comparison loop changes "1" every step, when the maximum oscillation frequency of the voltage-controlled oscillator 5 is necessary, Next, it is necessary to change the count value of the up-and-down counter 8 to the maximum value, but for this it is necessary to repeat 2 M Times (M is the number of bits of the up-down counter 8) the frequency comparison in the frequency comparator 7, there is the problem that the locking time of the double-loop PLL becomes long

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