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Method for generating design constraints for modulates in hierarchical integrated circuit design system

A technology for integrated circuit and circuit design, applied in the field of design constraints for generating modules in a hierarchical integrated circuit design system, can solve problems such as inability to measure realizability, inability to achieve timing closure, etc.

Inactive Publication Date: 2004-10-20
美格马自动控制设计公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Failure to measure achievability is the biggest problem facing design teams today and is the main reason for the inability to achieve timed closure experienced in contemporary design methodologies

Method used

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  • Method for generating design constraints for modulates in hierarchical integrated circuit design system
  • Method for generating design constraints for modulates in hierarchical integrated circuit design system
  • Method for generating design constraints for modulates in hierarchical integrated circuit design system

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Embodiment Construction

[0027] One way to implement a top-down hierarchical design process is as figure 2 The hierarchical design flow chart is shown. figure 2 The design flow chart shown is figure 1 A modification of the top-down flowchart shown in which three steps 230, 260, and 265 are added. The improvements described relate to the method for modeling a child block in the context of its parent and sibling blocks during the top-down budget and block realization steps and the bottom-up verification step. These steps indicate in the flowchart where clear hierarchical boundaries are violated requiring cross-boundary analysis. Without effective techniques for managing such cross-boundary analysis, the main advantages of hierarchical design processing - the ability to reduce the memory and runtime required to design large-scale integrated circuits - would be lost.

[0028] During the top-down budgeting step, one goal is to analyze combined logic paths (combined logic gates between registers (latch...

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Abstract

What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a timing budget by examining said estimated arrival times at said blocks pins.

Description

Background technique [0001] In electronic computer-aided design (ECAD) software systems, integrated circuit design specifications and implementation data must be stored as a set of database records with some finite maximum size. Furthermore, the execution time of ECAD software generally increases with the size of the design. The data representing a very large integrated circuit design may be too large to fit in the computer's memory, or the execution time required to design or simulate the entire design may be unacceptable. This is especially true when the number of elements (ie, gates) and accompanying connections within an integrated circuit is on the order of tens of millions or tens of millions. [0002] Hierarchical decomposition or "partitioning" is a technique that can be used to reduce the complexity of large integrated circuit design specifications so that the memory and / or execution time required to complete the design remains manageable, instead of representing th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50H01L21/82H01L21/822H01L27/04
CPCG06F17/5045G06F17/505G06F17/5022G06F17/5031G06F30/3312G06F30/30G06F30/327G06F30/33G06F2119/12G06F30/3315
Inventor 蒂莫西·M.·布尔克斯迈克尔·A.·瑞普海密德·萨沃扎罗伯特·M.·斯旺森卡恩·E.·瓦特拉路卡斯·梵·金尼肯
Owner 美格马自动控制设计公司