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Forming a semiconductor structure using a combination of planarizing methods and electropolishing

An electrolytic polishing and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc.

Inactive Publication Date: 2004-11-03
ACM RES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the presence of strong mechanical forces, the CMP method has several detrimental effects on the underlying semiconductor structure

Method used

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  • Forming a semiconductor structure using a combination of planarizing methods and electropolishing
  • Forming a semiconductor structure using a combination of planarizing methods and electropolishing
  • Forming a semiconductor structure using a combination of planarizing methods and electropolishing

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Embodiment Construction

[0017] The following description sets forth numerous specific details, such as specific materials, parameters, etc., in order to provide a more complete understanding of the present invention. It should be realized, however, that these descriptions are not intended as limitations on the scope of the invention, but rather as a better illustration of exemplary embodiments.

[0018] Chemical-mechanical polishing (CMP) is a known method for planarizing and polishing semiconductor surfaces, however, CMP can produce stress-related defects on the underlying structure, eg, dishing, erosion, film bumping, scratching, etc. In contrast, electropolishing is a process of polishing metals (eg, copper) that provides a relatively stress-free polishing method. However, as described below, electropolishing is an isotropic etching method, ie it etches the metal layer at approximately the same rate regardless of height differences. Thus, if the metal layer layout profile or general shape is non-...

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Abstract

A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to previously filed Provisional Application U.S. Serial No. 60 / 313,086, filed August 17, 2001, entitled AMETHOD TO PLANARIZE COPPER DAMASCENE STRUCTRUEUSING A COMBINATION OF CMP AND ELECTRO-POLISHNG, the entire contents of which are here incorporated by reference. technical field [0003] The present invention relates generally to semiconductor devices and, more particularly, to methods of planarizing damascene structures using a combination of planarization methods and electrolytic polishing. Background technique [0004] Semiconductor devices are processed or manufactured by using a number of different process steps to create transistors and interconnect components. To electrically connect transistor terminals associated with a semiconductor die, conductive trenches, vias, etc. are formed in the dielectric material that is part of the semiconductor device. Trench a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C25F3/22B23H5/08B24B37/04C25F3/16C25F3/30H01L21/304H01L21/3205H01L21/321H01L21/3213H01L21/768
CPCH01L21/32134B23H5/08H01L21/7684B24B37/04H01L21/32136H01L21/32115C25F3/16H01L21/3212H01L2924/0002H01L2924/00H01L21/302
Inventor 姚向宇张如皋易培豪王晖
Owner ACM RES
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