Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier

A technology of voltage generators and amplifiers, which is applied in the field of integrated memory, and can solve the problems of reduced switching speed of read-write amplifiers, etc.

Inactive Publication Date: 2004-12-01
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, especially with regard to the supply voltage of the read-write amplifiers of integrated memories, it is also true that a smaller supply voltage for reduced power consumption also produces a reduction in the switching speed of the associated read-write amplifiers if the read-write amplifiers used for access and amplification operations Amplifiers are activated using this lower supply voltage

Method used

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  • Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier
  • Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier
  • Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier

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Embodiment Construction

[0016] Figure 1 shows an illustration of a memory cell array of an integrated memory M, wherein memory cells MC are arranged along word lines WL0, WL1, WL2 and bit lines BL0, BL1, and memory cells MC are arranged on the bit lines BL0, BL1 and the Intersection of word lines WL0, WL1, WL2. In this example embodiment, only a limited number of word lines and bit lines are shown for the sake of clarity, but in reality the integrated memory has many word lines and bit lines. Each memory cell MC includes a storage capacitor C, which is connected to one of the bit lines BL0, BL1 via a selection transistor AT. , WL2 is turned on, and as a result, the data signal can then be read from or written to the selected memory cell. The data signal of the selected memory cell is present on the associated bit line BL0, BL1 and is accessed and amplified in one of the illustrated read / write amplifiers SA0, SA1.

[0017] During the operation of reading a data signal from one of the memory cells, t...

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Abstract

An integrated memory contains a memory cell array, which has word lines and bit lines, and a read / write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read / write amplifier. A potential difference is applied to the read / write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read / write amplifier for a limited period of time during an assessment and amplification operation of the read / write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

Description

technical field [0001] The present invention relates to an integrated memory with an array of memory cells, which has word lines for selecting memory cells and bit lines for reading or writing data signals, and also has read and write amplifiers connected to the bit lines to perform The purpose of accessing and amplifying data signals. A voltage generator circuit is further provided to generate a supply voltage applied to the read-write amplifier. Background technique [0002] An integrated memory, such as in the form of a DRAM, generally has an array of memory cells including word lines and bit lines. In this case, the memory cell is arranged at the intersection of the bit line and the word line. The memory cell is fabricated in particular from a storage capacitor and a selection transistor connecting the individual storage capacitor to one of the bit lines, the control terminal of which is individually connected to one of the word lines for selecting the memory cell the...

Claims

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Application Information

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IPC IPC(8): G11C7/06G11C11/4091
CPCG11C11/4091G11C2207/065G11C7/06
Inventor R·施奈德J·沃而拉思M·格纳特
Owner INFINEON TECH AG
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