Semiconductor device and method for evaluating characteristics of the same

An evaluation method, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, semiconductor/solid-state device testing/measurement, etc., can solve problems that cannot represent the distribution of the main characteristics of semiconductor integrated circuits, and excessively strict management of manufacturing conditions, etc.

Inactive Publication Date: 2004-12-01
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In other words, it cannot represent the characteristic distribution of the main body of the semiconductor integrated circuit, so it may cause excessive strict management of manufacturing conditions

Method used

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  • Semiconductor device and method for evaluating characteristics of the same
  • Semiconductor device and method for evaluating characteristics of the same
  • Semiconductor device and method for evaluating characteristics of the same

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Experimental program
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no. 1 Embodiment approach

[0036] —Structure of the Evaluation Department—

[0037] figure 1 (a) and (b) respectively show a plan view of an evaluation unit in the semiconductor device according to the first embodiment, and an I-I line cross-sectional view of one MIS transistor for evaluation in the evaluation unit, respectively.

[0038] Such as figure 1 As shown in (a) and (b), the evaluation section is configured by arranging MIS transistors TrA, TrB, and TrC for evaluation, which are elements for characteristic evaluation, on the three active regions RacA, RacB, and RacC surrounded by the trench element isolation 11. . Furthermore, the common gate electrode 17 is provided on the three evaluation MIS transistors TrA to TrC. In addition, the evaluation section further includes a source pad 12 (common conductor portion for source) electrically connected to the respective source regions 15 of the three MIS transistors TrA-TrC for evaluation, and a source pad 12 (common conductor portion for source)...

no. 2 Embodiment approach

[0053] Figure 4 (a) and (b) are respectively a plan view of the evaluation unit of the semiconductor device according to the second embodiment and a cross-sectional view of one MIS transistor for evaluation in the evaluation unit taken along line IV-IV, respectively.

[0054] Such as Figure 4 As shown in (a) and (b), in the present embodiment, the evaluation unit arranges the evaluation MIS transistors TrA, TrA, and TrB, TrC constituted. Furthermore, the common gate electrode 17 is provided on the three evaluation MIS transistors TrA to TrC. In addition, the evaluation section further includes source pads 12 electrically connected to the source regions 15 of the three MIS transistors TrA to TrC for evaluation, and pads 12 electrically connected to the drain regions 16 of the three MIS transistors TrA to TrC for evaluation. The drain pad 13 and the gate pad 14 are electrically connected to the common gate electrode 17 on the three evaluation MIS transistors TrA to TrC.

...

no. 3 Embodiment approach

[0063] Figure 5 (a) and (b) are, respectively, a plan view of an evaluation unit in the semiconductor device according to the third embodiment, and a cross-sectional view of one of the evaluation MIS transistors in the evaluation unit taken along line V-V.

[0064] Such as Figure 5 As shown in (a) and (b), in this embodiment, the evaluation unit is configured by arranging the evaluation MIS transistor TrA, which is the element for characteristic evaluation, on the three active regions RacA, RacB, and RacC surrounded by the trench element isolation 11. , TrB, TrC. Furthermore, the common gate electrode 17 is provided on the three evaluation MIS transistors TrA to TrC. In addition, the evaluation section further includes source pads 12 electrically connected to the source regions 15 of the three MIS transistors TrA to TrC for evaluation, and pads 12 electrically connected to the drain regions 16 of the three MIS transistors TrA to TrC for evaluation. The drain pad 13 and th...

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Abstract

A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Description

technical field [0001] The present invention relates to a semiconductor device provided with an element for characteristic evaluation in addition to an actual operating element and a method for evaluating its characteristic. Background technique [0002] In the past, in semiconductor devices, in order to easily detect characteristics abnormalities caused by dispersion deviations in manufacturing characteristics and process failures without probing products, a device capable of measuring contact resistance, threshold voltage of transistors, and Elements for measuring characteristics such as I-V characteristics. [0003] Figure 11 (a), (b), and (c) respectively show a circuit diagram, a plan view, and a cross-sectional view of an evaluation section of a conventional element for characteristic evaluation, respectively. [0004] Such as Figure 11 As shown in (a) and (b), the evaluation section includes: a MIS transistor 101 which is an element for characteristic evaluation, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L23/544H01L27/088H01L29/78
CPCY10S257/919H01L27/088H01L22/34H01L2924/0002H01L2924/00
Inventor 安井孝俊柁谷敦宏
Owner PANASONIC CORP
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