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Semiconductor device, method of manufacturing semiconductor device, semiconductor chip, electronic module and electronic equipment

A semiconductor and chip technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as difficult contact, achieve wide spacing and prevent contact

Inactive Publication Date: 2005-06-15
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the alignment error between the electrode and the lead is considered, there is a limit to narrowing the pitch
If the electrode pitch of the semiconductor chip is narrow, it is difficult to keep the leads from contacting the electrodes adjacent to the connected electrodes

Method used

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  • Semiconductor device, method of manufacturing semiconductor device, semiconductor chip, electronic module and electronic equipment
  • Semiconductor device, method of manufacturing semiconductor device, semiconductor chip, electronic module and electronic equipment
  • Semiconductor device, method of manufacturing semiconductor device, semiconductor chip, electronic module and electronic equipment

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0041] figure 1 It is a figure explaining the semiconductor device of Embodiment 1 of this invention. figure 2 Yes figure 1 An enlarged view of a portion surrounded by a dashed-dotted line of the semiconductor device shown. image 3 Yes figure 2 The III-III line sectional view is shown.

[0042] The semiconductor device has a semiconductor chip 10 . The semiconductor chip 10 may also have a shape (cuboid) having a rectangular surface. An integrated circuit 12 is formed in the semiconductor chip 10 . A passivation film (electrical insulating film) not shown may also be formed so as to cover the integrated circuit 12 .

[0043] The semiconductor chip 10 has a line along the first line L 1 A first set of electrodes 14 is arranged. The first set of electrodes 14 are arranged in a row. The first straight line L 1 , may also be a straight line parallel to the edge of the semiconductor chip 10 (for example, the long side of the rectangular surface). The first group of el...

Embodiment approach 2

[0068] Figure 5 It is a figure explaining the semiconductor device of Embodiment 2 of this invention. The same terms (excluding symbols) as those used in Embodiment 1 correspond to the same contents. In this embodiment, the second group of electrodes 52 is divided into 1 Parallel straight lines (such as the third and fourth straight lines L 3 , L 4 ) arranged multiple sets of electrodes (for example, the third and fourth sets of electrodes 53, 54) are arranged.

[0069] by a pair of second straight lines L 2 In each region 58 of clamping, at least 1, or 2, or more than 2 ( Figure 5 2) electrodes 53. In each area 58, at least one of the fourth group ( Figure 5 is 1) electrode 54. In each area 58, the pair of electrodes 53 of the third group is sandwiched and in contact with it, and are aligned with the first straight line L. 1 Orthogonal pair of fifth straight lines L 5 At least one electrode 54 of the fourth group is arranged in a sandwiched manner.

[0070] Exce...

Embodiment approach 3

[0072] Image 6 It is a figure explaining the semiconductor device of Embodiment 3 of this invention. The same terms (excluding symbols) as those used in Embodiment 1 and Embodiment 2 correspond to the same contents. In this embodiment, the second group of electrodes 62 is divided into 1 Parallel straight lines (such as the third and fourth straight lines L 3 , L 4 ) arranged multiple sets of electrodes (for example, the third and fourth sets of electrodes 63, 64) are arranged.

[0073] by a pair of second straight lines L 22 In each region 68 of clamping, at least 1, or 2, or more than 2 ( Image 6 4) electrodes 63. In each area 68, at least 1 or 2, or more than 2 ( Image 6 2) electrodes 64. In each region 68, a pair of adjacent electrodes 63 of the third group are sandwiched and connected thereto, and are aligned with the first straight line L. 1 Orthogonal pair of fifth straight lines L 55 clamping manner, arranged at least one of the fourth group ( Image 6 1) ...

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Abstract

The present invention provides a semiconductor device in which 2 or 2 of the second group are respectively arranged in a plurality of regions (18) divided by a plurality of second straight lines (L2) orthogonal to the first straight line (L1). The above electrode (16). Each region (18) is a region sandwiched by a pair of second straight lines (L2) sandwiching and contacting a pair of adjacent electrodes (14) of the first group. The semiconductor chip (10) is mounted on the substrate (20) in such a manner that the first set of electrodes (14) faces the first set of leads (22), and the second set of electrodes (16) faces the second set of leads (24). )superior. Each lead wire (24) of the second group is arranged passing between the lead wires (22) of the first group. This prevents the lead wire from coming into contact with the electrode.

Description

[0001] technology area [0002] The present invention relates to a semiconductor device and a manufacturing method thereof, a semiconductor chip, an electronic component, and electronic equipment. Background technique [0003] In mounting forms such as COF (Chip On Film), leads are electrically connected to electrodes of a semiconductor chip. In recent years, the pitch of electrodes has become narrower, and the pitch of lead wires has to be narrowed accordingly. However, if the alignment error between electrodes and leads is considered, there is a limit to narrowing the pitch. If the electrode pitch of the semiconductor chip is narrow, it is difficult to keep the leads from contacting the electrodes adjacent to the electrodes to which they are connected. [0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 7-235564 [0005] [Patent Document 2] Japanese Unexamined Patent Publication No. 7-273119 Contents of the invention [0006] The purpose of the prese...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/498
CPCH01L23/49838H01L23/4985H01L2924/0002H01L2924/00
Inventor 漆户达大
Owner SEIKO EPSON CORP