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Receiving apparatus

A technology for a receiving device and a clock signal, which is applied to synchronization devices, channel distribution devices, automatic power control, etc., and can solve problems such as increasing circuit area.

Inactive Publication Date: 2005-12-14
THINE ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0023] However, as in prior art 2 above, although each channel circuit block has the same structure, configuring them one by one causes a problem that the circuit area increases approximately in proportion to the increase in the number of channels.

Method used

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no. 1 Embodiment

[0098] First, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 12 is a functional block diagram showing the configuration of receiving apparatus 5000 of this embodiment. In addition, in FIG. 12, in the receiving apparatus 5000 for receiving serially transmitted data of 3 channels, by setting the number of symbol bits of the symbol sampling clock signal to 10 bits, the equivalent of the 4-fold oversampling method is realized. Or equivalent or better phasing capability.

[0099] As shown in FIG. 12, the receiving apparatus 5000 of the present embodiment includes a common circuit 2 and three demodulation circuits 3A, 3B, and 3C. In such a configuration, the configuration of the common circuit 2 is the same as that explained in FIG. 11 , and inputs the calibration measurement clock signal 24 to the demodulation circuits 3A, 3B, and 3C, respectively.

[0100] In addition, any one of demodulation circuits 3A, 3B, and 3C (...

no. 2 Embodiment

[0103] Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 13 is a functional block diagram showing the configuration of receiving apparatus 6000 of this embodiment. In addition, in FIG. 13, in the receiving apparatus 6000 for receiving serially transmitted data of 3 channels, by setting the number of symbol bits of the symbol sampling clock signal to 10 bits, the equivalent of the 4-fold oversampling method is realized. Or equivalent or better phasing capability.

[0104] As shown in FIG. 13, receiving apparatus 6000 of the present embodiment includes common circuit 2, common synchronization circuit 2A, and three demodulation circuits 3D, 3E, and 3F. In such a configuration, the configuration of the common circuit 2 is the same as that explained in FIG. 11 .

[0105] Furthermore, in order to share the DLL 30 provided in the demodulation circuit 3 shown in FIG. 11 among a plurality of demodulation circuits, the ...

no. 3 Embodiment

[0107] Next, a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 14 is a functional block diagram showing the configuration of receiving apparatus 7000 of this embodiment. In addition, in FIG. 14, in the receiving apparatus 7000 for receiving serially transmitted data of 3 channels, by setting the number of symbol bits of the symbol sampling clock signal to 10 bits, the equivalent of the 4-fold oversampling method is realized. Or equivalent or better phasing capability.

[0108] As shown in FIG. 14, the receiving apparatus 7000 of this embodiment has a common circuit 2 and three demodulation circuits 3G, 3H, and 3J. In such a configuration, the configuration of the common circuit 2 is the same as that explained in FIG. 11 .

[0109] In addition, any one of the demodulation circuits 3G, 3H, and 3J (here, assumed to be 3G) has the same configuration as that of the demodulation circuit 3 shown in FIG. 11 . In addition, oth...

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Abstract

The receiving device (5000) has a common circuit (2) and three demodulation circuits (3A, 3B, 3C). The demodulation circuit (3A) has a second synchronization circuit (30), a clock selection circuit (25), a sampling register (28), a calibration calculation circuit (40), a decoding circuit (50), and a local buffer (26). In addition, the second synchronization circuit (30) has a phase detector, a low-pass filter (32), and a voltage-controlled delay circuit (33). The other demodulation circuits (3B, 3C) share the configuration of the phase detector (31) and the low-pass filter (32) in the second synchronization circuit (30) of the demodulation circuit (3A). Therefore, it is unnecessary to provide a phase detector (31) and a low-pass filter (32) in the second synchronous circuit (30a) in the demodulation circuits (3B, 3C), thereby reducing the circuit area.

Description

technical field [0001] The present invention relates to a receiving device for serial digital transmission signals, in particular to a receiving device for demodulating serially transmitted data. Background technique [0002] In recent years, in receiving circuit devices for high-speed digital transmission signals, when performing data demodulation, the serial data is generally sampled by using an equal-phase symbol sampling clock signal. The sampling clock signal and the serialized Transmission clock signals with the same number of symbol bits are synchronized. [0003] On the other hand, in the demodulation circuit of this simple sampling method, even if the symbol sampling clock signal is used to correctly sample the transmission data, the deviation of the signal delay on the transmission line causes the data phase to sample the symbol. When the clock signal is skewed (skew), or when the waveform of the transmission signal itself is degraded due to signal delay variation...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/04H03L7/07H03L7/081H04L7/033H04L25/14
CPCH03L7/07H03L7/0805H03L7/0816H04L7/0337H04L25/14
Inventor 冈村淳一
Owner THINE ELECTRONICS
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