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FIFO data buffering method and full up space accessing FIFO memory

A first-in-first-out and data cache technology, which is applied in the field of full-space first-in-first-out memory, can solve the problems that valid data cannot be read out, and full space cannot be written.

Inactive Publication Date: 2006-02-08
VIMICRO CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the process of software operation, when A2=A1-1, no more write operations are allowed, so that there is an address that has not been written with valid data, so that the full space cannot be written
The situation of reading is the same, assuming that the read address A1=A2-1, there is also a valid data that cannot be read

Method used

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  • FIFO data buffering method and full up space accessing FIFO memory
  • FIFO data buffering method and full up space accessing FIFO memory
  • FIFO data buffering method and full up space accessing FIFO memory

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Embodiment Construction

[0021] The present invention will be described in detail below with reference to the accompanying drawings. It is worth emphasizing that the following embodiments are only for making the description of the present invention clearer and easier to understand, rather than limiting the present invention.

[0022] Figure 4 A schematic block diagram of a full-space first-in-first-out memory (FIFO) with a storage capacity of 2m·n bits according to the present invention is given. The present invention will be described below by taking the design of a 128*32 full space read-write FIFO as an example. Such as Figure 5 As shown, the 128*32 full space access first-in-first-out memory includes dual-port RAM, 8-bit counter A and counter B, and a read enable generation circuit and a write enable generation circuit. In this embodiment, the data bus width of the dual-port RAM 1 is 32 bits; the address bus width is 7 bits, that is, there are 128 addresses. Among them, the dual-port RAM can ...

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Abstract

The invention relates to a method of first-in first-out data buffer and a full space visiting first-in first-out storage. It adopts two m+1 bit counters and connects the low m bit of the counter with the double port storage address bus; it compares the m+1 bit output of the two m+1 bit read / right counters to separately generate write and read starting signal, when the write starting signal defeats, the full space stores the effect signal, when the read starting signal defeats, it reads all of the full space effect data so as to fully use the storage space of the double port storage.

Description

technical field [0001] The invention relates to a first-in-first-out storage method and device, in particular to a full-space first-in-first-out storage. Background technique [0002] In digital circuits, memory has a very wide range of uses, the most important of which is to store data. According to the order of data access operations, memory can be divided into random read-write memory (RAM) and first-in-first-out memory (FIFO). , Stack memory (FILO). Random read-write memory can read and write any storage space within the addressing range within one operation cycle. This kind of memory is used in occasions where reading and writing are very frequent and the order of operations is not required. The stack memory can also be called the first-in first-out memory, and its operation sequence is that the data written initially can only be read out last, such as writing the three numbers 0x11, 0x22, and 0x33 into the stack memory, first write 0x11, and then 0x22, and finally 0x...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/00G06F12/00
Inventor 杨柱刘健
Owner VIMICRO CORP
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