Integrating metal with ultra low-K dielectrics

Abstract

In forming a layer of a semiconductor wafer ( 100 ), a dielectric layer is deposited on the semiconductor wafer. The dielectric layer ( 204 ) includes material having a low dielectric constant. Recessed ( 210 ) and non-recessed ( 211 ) areas are formed in the dielectric cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.

Description

[0001] Cross-parameters to related applications [0002] This application claims priority to an earlier filed provisional application U.S. Ser. No. 60 / 233,587, entitled "Methods of Integrating Copper and Ultra-Low-K Dielectrics," filed September 18, 2000, in its entirety Introduced here for arguments. technical field [0003] The present invention relates generally to interconnects within layers of semiconductor wafers, and more particularly, the present invention relates to interconnects in low-k dielectric materials and ultra-low-k dielectric materials. Background technique [0004] Generally, semiconductor devices are fabricated on circular slices of semiconductor material known as wafers or slices. More specifically, a wafer is first diced from a silicon rod, and the silicon wafer is then subjected to multiple masking, etching, and deposition processes to form the electronic circuitry of the semiconductor device. [0005] Over the past few decades, the semiconductor in...

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Problems solved by technology

However, building such a structure in a low-k dielectric material would be expensive and would increase interconnection delays within the device, which is what the low-k dielectric material is intended to reduce

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