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Method for forming structures in finFET devices

A technology of fins and devices, which is applied in the field of forming fin field effect transistor devices, can solve problems that are difficult to overcome, difficult to master, compatibility, and mobility reduction.

Active Publication Date: 2006-05-03
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] For example, when the gate length of a conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) is less than 100nm, problems such as excessive leakage between the source and drain caused by short-channel effects become more and more difficult to overcome
In addition, the reduction of mobility and many process problems also make it difficult for traditional MOSFETs to grasp the compatibility of device characteristics with decreasing size.

Method used

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  • Method for forming structures in finFET devices
  • Method for forming structures in finFET devices
  • Method for forming structures in finFET devices

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Embodiment Construction

[0014] Embodiments according to the present invention will be described in detail with reference to the drawings. In different drawings, the same reference numerals may designate the same or similar elements, and the following detailed description is not intended to limit the invention, but rather, the scope of the invention is defined by the claims and their equivalents.

[0015] Embodiments in accordance with the principles of the present invention provide a single crystal silicon fin structure formed on opposite sides of a dielectric fin structure. The material of the dielectric fin structure is selected to induce effective stress in the single crystal silicon material to enhance mobility.

[0016] Figure 1 illustrates a typical method for forming the fin structure of a FinFET device in an embodiment in accordance with the principles of the present invention. Figure 2 to Figure 9 A typical view of a FinFET device fabricated according to the method shown in FIG. 1 is shown....

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Abstract

A semiconductor device, comprising a first fin structure (810), a second fin structure (810) and a third fin structure (210). The first and second fin structures (810) include single crystal silicon material. The third fin structure (210) is located between the first and second fin structures (810) and includes a dielectric material. The third fin structure (210) generates stress induced to the single crystal silicon material in the first and second fin structures (810).

Description

technical field [0001] The present invention relates generally to semiconductor fabrication, and more particularly to forming Fin Field Effect Transistor (FinFET) devices. Background technique [0002] With the increasing demand for high density and high performance in the field of ultra-large-scale integrated semiconductor devices, design features such as gate length are required to be less than 100nm, with high reliability performance and increasing productivity. After the design feature size (design features) is reduced to below 100nm, it challenges the limit of traditional methodology. [0003] For example, when the gate length of a conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) is less than 100nm, problems such as excessive leakage between the source and drain caused by short-channel effects become It's getting harder and harder to overcome. In addition, the reduced mobility and many process-handling issues also make it difficult for tr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/20H01L21/8234H01L27/088H01L29/786
CPCH01L21/823412H01L21/823437H01L27/088H01L29/66795H01L29/7842H01L29/785H01L21/18
Inventor 林明仁汪海宏俞斌
Owner ADVANCED MICRO DEVICES INC