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Semiconductor memory device

A storage device, semiconductor technology, applied in the direction of input/output to record carrier, preventing unauthorized use of memory, instrument, etc., can solve the problems of low data transmission efficiency, high security intensity, weak security intensity, etc., and achieve readout performance Excellent, high-efficiency safety strength, the effect of strengthening safety

Active Publication Date: 2006-05-10
MEGACHIPS +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Patent Document 1 is a security method using scrambling, which has the advantage of high data transmission efficiency, but the disadvantage is that the security strength is usually weak
However, Patent Document 2 or Patent Document 3 is a one-step logic operation using a logic circuit, which has the advantage of fast processing, but the disadvantage is that if you know which logic circuit is used, it is easy to be analyzed, so the confidentiality is low
The advantage of this encryption method is that it has high security strength, but the disadvantage is that the transmission efficiency of data is reduced.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0039] Next, the structure of the semiconductor memory 10 of the first embodiment will be described. figure 2 is a circuit block diagram of the semiconductor memory 10 . The semiconductor memory 10 includes a memory core unit 11 and an input / output terminal unit 12 , and by inserting a memory unit control unit 13 between the memory core unit 11 and the input / output terminal unit 12 , data stored in the memory core unit 11 is secured.

[0040] The input / output terminal unit 12 includes a command input terminal for inputting a command supplied from the information processing device 1 and a data output terminal for outputting data read from the memory core unit 11 . A command supplied through a command bus (also generally referred to as an address bus) is input from the information processing device 1 to a command input terminal. The data output terminal is connected to the data bus of the information processing device 1 .

[0041] In addition, if the information processing de...

Embodiment 2

[0097] Next, the structure of the semiconductor memory 10A of the second embodiment will be described. Figure 5 is a block diagram of the semiconductor memory 10A. Note that the description of the same components as those in the first embodiment is omitted.

[0098] The semiconductor memory 10A in the second embodiment differs from the first embodiment in that the data scramble circuit 133 is not provided in the memory control unit 13A, but the command descramble circuit 136 is provided. That is to say, in Embodiment 2, the structure is such that no bit operation is applied to the data read from the memory core section 11, and if the command supplied from the information processing device 1 is encrypted, it is decoded; if it is scrambled by the command , then descramble it. In addition, the descrambling value is set in the register 135 .

[0099] The command descrambling circuit 136 is a circuit for descrambling the command supplied from the information processing device 1...

Embodiment 3

[0126] Next, the structure of the semiconductor memory 10B of the third embodiment will be described. Figure 7 It is a circuit block diagram of the semiconductor memory 10B, and the description of the same configuration as that of the first or second embodiment is omitted.

[0127] The semiconductor memory device 10B in the third embodiment is a combination of the first and second embodiments. Specifically, the memory control unit 13 has two circuits of a data scramble circuit 133 and a command descramble circuit 136 .

[0128] The semiconductor memory 10B in the third embodiment can switch between the two operation modes shown in Table 3. That is, in the first mode, the command descrambling circuit 136 is turned OFF, the command decoding circuit 131 is turned ON, and the data scramble circuit 133 is turned ON or OFF. In the second mode, the command descrambling circuit 136 is turned OFF, the command decoding circuit 131 is turned ON or OFF, and the data scramble circuit 13...

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PUM

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Abstract

The semiconductor memory 10 is provided with a memory control section 13 and a memory core section 11 . The command determination circuit 132 provided in the memory control unit 13 changes the operation mode of the semiconductor memory 10 according to a command sent from the control unit of the information processing device. In the first mode, the instruction decoding circuit 131 performs decoding processing without scrambling the data output from the memory core unit 11 . In the second mode, the instruction decoding circuit 131 scrambles the instruction output from the memory core unit 11 without performing decoding processing.

Description

technical field [0001] The present invention relates to semiconductor storage devices, and more particularly to the security of various data stored in semiconductor storage devices. Background technique [0002] An information processing device that provides a removable semiconductor memory and operates using data including a program stored in the semiconductor memory is known. Also, various structures for realizing the security of data stored in semiconductor memories have been proposed. [0003] Patent Document 1 discloses a technique for realizing data security by scrambling data output from a semiconductor memory using key data. [0004] In addition, Patent Document 2 or Patent Document 3 discloses a technique for realizing data security by encrypting address data output from a semiconductor memory or data output from a semiconductor memory using a logic circuit (Logic). [0005] Patent Document 1: Japanese Unexamined Patent Publication No. 9-106690 [0006] Patent Do...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/14G06F1/00G06F3/06G06F21/62G06F21/72G06F21/74G06F21/75G06F21/86
CPCG06F21/79G06F21/85
Inventor 山口育男梅津隆二
Owner MEGACHIPS
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