Field programmable gate array loading method

Abstract

Disclosed is a method for loading field programmable gate array, which comprises steps of: placing EPLD between CPU and FPGA; S5-1: starting to load; S5-2: detecting whether the loading is over or not, that is, stopping loading by judging the DONE signal of FPGA as end, and when judging the DONE signal of being not over, executing following steps: S5-3íóS5-4: Writing one byte data needed for loading into the loading data register of the EPLD once by CPU; S5-5: completing the loading of needed data to the FPGA by the internal logic of the EPLD; S5-6: delaying some time; repeating the S5-2 to S5-6 until finishing loading.

Description

technical field [0001] The invention relates to a method for loading files into field-programmable gate arrays (FPGA, field-programmable gate arrays), in particular to a method for loading files into FPGA by using an erasable programmable logic device (EPLD, erasable programmable logic device). Background technique [0002] A Field Programmable Gate Array (FPGA) is an erasable programmable read-only memory. Usually, when the board is powered on and initialized, relevant programs and data are loaded into the FPGA. After the FPGA is initialized, complex logic control can be completed to realize various business processing functions. Since FPGA is a logic chip that does not save data when power is off, it is required to be reloaded every time it is powered on, that is, to rewrite data into the FPGA chip so that it can work normally. [0003] name meaning nCONFIG Logic chip reset pin nSTATUS Logic chip reset complete status pin DONE ...

AI Technical Summary

Problems solved by technology

However, since the time for reading and writing FLASH is generally longer, the effective time of chip selection for each access to the EPLD register should also be longer

Moreover, the general data is loaded from the EPLD to the FPGA according to each BIT operation. When using this method to load, each time a BIT is loaded, the EPLD wil

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