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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of affecting time and resist time spent

Inactive Publication Date: 2006-08-16
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, resist removal by low-pressure oxygen ions has the problem of affecting time due to reduced speed
In addition, in order to form deep grooves, in the case of forming a thick resist, there is a problem that it takes more time to remove the resist.

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0046] refer to Figure 1 to Figure 8 , the semiconductor device according to Embodiment 1 of the present invention will be described.

[0047] exist figure 1 In , a schematic cross-sectional view of an end portion of the semiconductor device according to this embodiment is shown. The semiconductor device of this embodiment is a semiconductor chip. figure 1 It is a schematic cross-sectional view of the corner portion of the chip. exist figure 1 In , arrow 47 shows the outside of the semiconductor device, and arrow 46 shows the inside of the semiconductor device. The circuit formation region is arranged on the side indicated by the arrow 46

[0048] In the semiconductor device of the present embodiment, a laminated body 41 a including a plurality of interlayer insulating films is formed on the upper surface of the silicon substrate 33 . A laminated body 42 including a plurality of interlayer insulating films formed of a low dielectric constant material is formed on the up...

Embodiment approach 2

[0105] reference from Figure 9 to Figure 13 , the semiconductor device according to Embodiment 2 of the present invention will be described. In the semiconductor device of the present embodiment, the seal ring is formed around the circuit formation region, and the groove portion is formed outside the seal ring, which is the same as in the first embodiment. The planar shape of the semiconductor chip as the semiconductor device is substantially quadrangular, as in the first embodiment.

[0106] exist Figure 9 In , a schematic cross-sectional view of a corner portion of the chip of the first semiconductor device according to the present embodiment is shown. In the first semiconductor device, the seal ring 25 has a shape in which corners are chamfered in a planar view of the corners of the chip. That is, in the corner portion of the chip, the seal ring 25 is formed opposite to the corner and extended. In the chip corner, the seal ring 25 is formed to be inclined with respect...

Embodiment approach 3

[0121] refer to Figure 14 to Figure 19 with Figure 7 , the semiconductor device according to Embodiment 3 of the present invention will be described.

[0122] Figure 14 It is a schematic cross-sectional view of the end portion of the semiconductor device of the present embodiment. A laminated interlayer insulating film 41 a , a laminated low dielectric constant film 42 , a laminated interlayer insulating film 41 b , and a surface protection film 43 are sequentially formed on the surface of the silicon substrate 33 , as in Embodiment 1. Formation of the seal ring 23 around the circuit formation region is also the same as in the first embodiment. The direction indicated by arrow 46 is an inner direction of the semiconductor device, and the direction indicated by arrow 47 is an outer direction of the semiconductor device.

[0123] In the semiconductor device of the present embodiment, the notch portion 28 is formed as a concave portion. In the surface of the semiconductor...

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PUM

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Abstract

A semiconductor device includes a low dielectric constant film having a copper interconnection formed therein, a silicon oxide film arranged above the low dielectric constant film, a surface protection film arranged above the silicon oxide film, a sealing ring formed to surround a circuit forming region, and a groove portion formed outside the sealing ring when viewed two-dimensionally. The groove portion is formed such that its bottom portion is located above the low dielectric constant film and such that the bottom portion is located below an upper end of the copper interconnection.

Description

technical field [0001] The present invention relates to a semiconductor device. Background technique [0002] Due to progress in the miniaturization of semiconductor devices, the parasitic capacity of the copper wiring has become equal to the input and output capacity of the transistor itself, which hinders the speeding up of device operation. Therefore, the introduction of silicon oxide (SiO 2 , Dielectric constant k4) The insulating film with a smaller dielectric constant. As an insulating film having a small dielectric constant, an insulating film of organic quartz glass (SiOC) containing carbon or hydrogen in silicon oxide is mainly used. The dielectric constant of an organic silica glass-based insulating film is about 3.3 or less, and a film having a dielectric constant k of 3.3 or less is called a low dielectric constant film in the present invention. [0003] In a semiconductor device, in order to prevent water from entering from the side and deteriorating the ope...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/00H01L23/58H01L23/522
CPCH01L23/3157H01L2924/0002H01L23/585H01L23/564H01L2924/00H01L21/31
Inventor 古泽健志松本雅弘森本升松浦正纯
Owner RENESAS TECH CORP