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Topological structure optimization method of clock tree

A technology of topology structure and optimization method, applied in the field of electronics, to achieve the effect of strong versatility, reduced cost and good scalability

Inactive Publication Date: 2006-09-13
FUDAN UNIV
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  • Claims
  • Application Information

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Problems solved by technology

At present, there is no such optimization operation strategy in the world

Method used

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  • Topological structure optimization method of clock tree
  • Topological structure optimization method of clock tree
  • Topological structure optimization method of clock tree

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Embodiment Construction

[0045] Further illustrate the present invention below by specific embodiment:

[0046] On a SoC chip whose physical and electrical parameters are known, the positions of the clock source and the clock receiving endpoint set have been determined. After topological division by a certain method, the initial topological relationship of the clock tree is obtained, such as figure 2 shown.

[0047] During a bottom-up local correction optimization process, it is assumed that the current operating point is node x. First perform a "trial" right-turn operation on node x, and calculate the topology information of the changed nodes along the way until reaching the root node to find the cost increment of the whole tree. During the calculation process, the topology structure remains undisturbed. Then perform a similar "trial" left-turn operation on node x, and calculate the corresponding cost increment. Choose the smaller one from the two cost increments, and then judge whether it is po...

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Abstract

A method for optimizing topological structure of clock tree includes applying topological relation generated by any other method as input, carrying out only partial revision on structure of said topological relation in clock - structuring procedure for saving cost; starting up each optimization procedure from leaf node of clock tree, utilizing binary tree conversion operation to make partial adjustment on all nodes and carrying out procedure upwards to root for finishing optimization.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a topology optimization method based on local modification of a VLSI clock tree. technical background [0002] With the rapid development of integrated circuit design and manufacturing technology, integrated circuit technology has entered the ultra-deep submicron era, and high frequency, high speed, and low power consumption have become the goals that need to be achieved in chip design. The scale of high-frequency, high-performance integrated circuits such as system-on-chip (SoC) continues to expand, and the interconnection delay between devices on the chip far exceeds the intrinsic delay of the device, resulting in the increasing impact of the quality of the clock distribution circuit on the performance of SoC big. Therefore, when designing a clock distribution circuit, on the one hand, it is necessary to make the clock signal reach the clock receiving terminal ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCH04L41/12
Inventor 陆伟成付强曾璇赵文庆周电
Owner FUDAN UNIV