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Transistor including physical property-changing layer, method of operating transistor, and method of manufacturing transistor

A physical modification, transistor technology, applied in semiconductor/solid-state device manufacturing, applications, home appliances, etc., can solve the problems of FET threshold voltage reduction, FET characteristic degradation, and carrier mobility reduction, etc., to achieve thermal radiation and power. The effect of reducing power consumption and reducing the short channel effect

Inactive Publication Date: 2006-09-13
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the short channel effect, the threshold voltage of FET is significantly lowered and the carrier mobility is reduced
Moreover, the characteristics of FETs are degraded due to drain induced barrier lowering (DIBL)

Method used

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  • Transistor including physical property-changing layer, method of operating transistor, and method of manufacturing transistor
  • Transistor including physical property-changing layer, method of operating transistor, and method of manufacturing transistor
  • Transistor including physical property-changing layer, method of operating transistor, and method of manufacturing transistor

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Embodiment Construction

[0023] The present invention will now be described more fully with reference to the accompanying drawings, in which specific embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0024] A transistor according to the present invention will be described as follows.

[0025] refer to figure 1 , the insulating layer 42 is stacked on the substrate 40 . The substrate 40 may be a semiconductor substrate doped with predetermined conductive impurities, such as a silicon substrate doped with n-type impurities. For example, insulating layer 42 may be a thermal oxide layer. The first conductive layer pattern 44 a and the second conductive layer pattern 44 b are formed on the insulating layer 42 . The first conductive layer pattern 44a and the second conductive layer pattern 44b are separated from each other by a predetermined distance. One of the first and second conductive layer patterns 44a and 44b serves as a ...

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PUM

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Abstract

A transistor using a physical property-changing layer, a method of operating the transistor, and a method of manufacturing the transistor are provided. The transistor may include an insulation layer formed on a substrate, the first and second conductive layer patterns, the physical property-changing layer, a dielectric layer, for example, a high dielectric layer, and a gate electrode. The first and second conductive layer patterns may be spaced apart from each other on the insulation layer. The physical property-changing layer may be formed on a portion of the insulation layer between the first and second conductive layer patterns. The dielectric layer may be stacked on the physical property-changing layer and the gate electrode may be formed on the high dielectric layer.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a transistor using a physically modifying layer, a method of operating the transistor, and a method of manufacturing the transistor. Background technique [0002] With the development of semiconductor technology, the integration level of semiconductor devices has increased rapidly. As the degree of integration of semiconductor devices increases, the size of semiconductor elements such as field effect transistors (FETs) constituting the semiconductor devices decreases. When the size of the FET is reduced, the channel length between the source electrode and the drain electrode becomes shorter, resulting in the so-called short-channel effect. Due to the short channel effect, the threshold voltage of the FET is significantly lowered and the carrier mobility is reduced. Also, the characteristics of the FET are degraded due to drain ind...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/02H01L21/336
CPCH01L29/78681H01L29/7869H10N99/03A47F1/12A47F13/00A47F7/28
Inventor 赵重来柳寅儆赵成逸
Owner SAMSUNG ELECTRONICS CO LTD