Memory rank decoder for a multi-rank dual inline memory module(DIMM)

Abstract

The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).

Description

technical field [0001] The present invention generally relates to a memory rank decoder (Memory Rank Decoder) for a dual in-line memory module (DIMM), and in particular to a memory rank decoder for a registered dual in-line memory module (DIMM) . Background technique [0002] A storage module is provided for increasing the storage capacity of the computer system. Initially, single in-line memory modules (SIMMs) were used in personal computers to increase storage capacity. A single in-line memory module includes DRAM chips on only one side of its printed circuit board (PCB). Contacts on the printed circuit board for connecting to a single in-line memory module (SIMM) are redundant on both sides of the module. The first variant of the SIMM has thirty pins and provides 8 bits of data (9 bits in a parity scheme). A second variant of the SIMM (known as PS / 2) includes 72 pins and provides 32 bits of data (36 bits in a parity scheme). [0003] Since memory modules in some proc...

AI Technical Summary

Problems solved by technology

However, there is a limit to the number of signal pins provided at the edge of the printed circuit board of a dual in-line memory module

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