Method for series and anti-series link data of equalizing complex strip parallel

Abstract

The present invention discloses preventing data transmission interrupted protection method in multitape parallel SERDES data links. It contains chip through detecting data frame to detect link status, when detecting error state, system stopping through error state occurring link transmitting data; when detecting data link get right, system recovering through said link transmitting data. The present invention ensures data transmission without interruption and automatic recovering full speed transmission in link get right through link status automatic-detection and balance in SERDES link parallel transmission scheme. The present invention also provides high-speed number reduced property and flexible configuration ability, in low service flow rate user capable of active switching off one or more link in parallel SERDES data link without influencing data regular transmission.

Description

technical field

[0001] The invention relates to a SERDES (Serialize and Deserialize, serial deserialize) link data protection method, in particular to a method for detecting multiple parallel SERDES link data and balancing services to links with normal states. Background technique

[0002] At present, the development of the digital communication field is advancing by leaps and bounds, and the data transmission rate between chips is also getting faster and faster. For 10 Gigabit routers, data streams are exchanged at a speed of 10Gbps. Currently, there are two types of interfaces that can achieve such a high speed: one is a dedicated standard interface, such as CSIX, SPI4, etc. This interface is generally a parallel bus with a separate clock that supports dynamic adjustment of the phase. However, due to the parallel bus and separate clocks, the number of buses is relatively limited, and a single line can only reach a speed of 1Gbps at most, so it is generally only used for ch...

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