Method for series and anti-series link data of equalizing complex strip parallel

A link data, plural technology, applied in the field of SERDES link data protection, can solve the problems of data loss, large delay, etc.

Active Publication Date: 2006-11-08
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] This method of software processing has a large delay, at least at the millisecond level. If the link status changes from good to bad, using this technology will cause a large amount of data loss (the peer end does not know the time of the link change. will continue to send data through the wrong link)
Conversely, if the link status changes from bad to good, this technology cannot quickly restore the data throughput capability

Method used

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  • Method for series and anti-series link data of equalizing complex strip parallel
  • Method for series and anti-series link data of equalizing complex strip parallel

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Embodiment Construction

[0030] Such as figure 1 , the data link consists of two SERDES parallel links, uplink 0 and uplink 1, respectively. Both the sending chip and the receiving chip have a sending control part and a receiving control part, and there is a channel connection from the receiving control part in the chip to the sending control part to transmit link state information. T0, T1, t0, and t1 in the figure are four SERDES sending units, and R0, R1, r0, r1 are four SERDES receiving units. The data channels in the uplink direction and downlink direction (the two SERDES links from left to right are the uplink direction, and the two SERDES links from right to left are the downlink direction) together form a complete bidirectional digital channel.

[0031] The reception of the link state is accomplished by relying on the SERDES reception control part. Such as figure 1 As shown, r0 and r1 can respectively detect the states of the uplink 0 and uplink 1 links, while R0 and R1 can respectively dete...

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Abstract

The present invention discloses preventing data transmission interrupted protection method in multitape parallel SERDES data links. It contains chip through detecting data frame to detect link status, when detecting error state, system stopping through error state occurring link transmitting data; when detecting data link get right, system recovering through said link transmitting data. The present invention ensures data transmission without interruption and automatic recovering full speed transmission in link get right through link status automatic-detection and balance in SERDES link parallel transmission scheme. The present invention also provides high-speed number reduced property and flexible configuration ability, in low service flow rate user capable of active switching off one or more link in parallel SERDES data link without influencing data regular transmission.

Description

technical field [0001] The invention relates to a SERDES (Serialize and Deserialize, serial deserialize) link data protection method, in particular to a method for detecting multiple parallel SERDES link data and balancing services to links with normal states. Background technique [0002] At present, the development of the digital communication field is advancing by leaps and bounds, and the data transmission rate between chips is also getting faster and faster. For 10 Gigabit routers, data streams are exchanged at a speed of 10Gbps. Currently, there are two types of interfaces that can achieve such a high speed: one is a dedicated standard interface, such as CSIX, SPI4, etc. This interface is generally a parallel bus with a separate clock that supports dynamic adjustment of the phase. However, due to the parallel bus and separate clocks, the number of buses is relatively limited, and a single line can only reach a speed of 1Gbps at most, so it is generally only used for ch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L69/14
Inventor 叶锦华孙浩
Owner HUAWEI TECH CO LTD
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