Level shift circuit and semiconductor integrated circuit having the same

Abstract

A level shift circuit comprises two N-ch transistors Tn1,Tn2 that receive a pair of complementary input signals; and two P-ch transistors Tp1,Tp2 that have their gate terminals cross-coupled to each other; wherein nodes A,B, which are the drains of the two N-ch transistors Tn1,Tn2 and which operate inversely to each other, are connected to each other at a resistor Tp3. The resistor Tp3, which comprises a P-ch transistor, has its gate grounded and is always conductive. For example, when the N-ch transistor Tn1 is turned on and the N-ch transistor Tn2 is turned off, a current initially flows from the node A exhibiting a higher potential through the resistor Tp3 to the node B exhibiting a lower potential, which results in a rise of the potential at the node B. Therefore, the potential rise at the node B is promoted as compared with a case where only the P-ch transistor Tp2 is turned on. Thus, the level shift circuit having a less number of elements can operate in a higher rate.

Description

technical field [0001] The present invention relates to a level shift circuit required in semiconductor integrated circuits having different power supply voltages. Background technique [0002] Next, a conventional level conversion circuit will be described. [0003] Figure 5 Indicates a conventional level conversion circuit. exist Figure 5 Among them, BUF1 is a buffer including inverters INV1 and INV2 working at a low power supply voltage, and BUF2 is a buffer including inverters INV3 and INV4 working at a high power supply voltage; VDDH is a high-voltage power supply , VDDL is the low-voltage power supply; VSSH is the ground (0V) for the high-voltage power supply, VSSL is the ground (0V) for the low-voltage power supply; Tn1 is the 1st N-channel (hereinafter referred to as Nch) MOS transistor, Tn2 is the 2nd N Channel (hereinafter referred to as Nch) MOS transistor; Tp1 is the first P channel (hereinafter referred to as Pch) MOS transistor, Tp2 is the second P channel ...

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Problems solved by technology

Furthermore, there is a problem that when the drains of the Nch MOS transistors Tn3, Tn4 are directly connected to the high-voltage power supply VDDH, due to the manufacturing process of the semiconductor element, the back gate (back gate) and the drain of these Nch MOS transistors Tn3, Tn4 must be adjusted. poles are reverse-biased by the magnitude of the high supply voltage VDDH, so their reliability is degraded

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