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Wafter level vacuum packaging method

A vacuum packaging, wafer-level technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of unsealable holes 721, limited thickness, and increased packaging costs

Inactive Publication Date: 2007-03-21
邹庆福
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Although the aforementioned packaging method can be packaged at the wafer level to increase the efficiency of the packaging process, when opening the hole 721 on the cover 72, the hole 721 must be controlled to a size of 1-2 microns or smaller. Otherwise, when the encapsulation layer 74 is vapor-deposited, the particles of the vapor-deposition material cannot fill the hole 721, and the hole 721 cannot be sealed. As a result, the tiny hole 721 needs to be opened with a high-level process, resulting in The cost of packaging increases
[0006] Furthermore, when the encapsulation layer 74 is vapor-deposited, the vapor-deposition material is a common metal, so the encapsulation layer 74 plated, such as an aluminum film, is less effective in resisting environmental erosion, and during vapor-deposition, its When the metal particles of the vapor deposition material are deposited on the cover 72, some metal particles will fall into the cover 72 from the hole 721 and deposit on the microstructure 71, thereby affecting the performance of the microstructure 71 and causing quality problems. bad
[0007] In addition, when removing the sacrificial layer around the microstructure 71 in the etching process, due to the limited thickness of the sacrificial layer between the cover 72 and the microstructure 71, the fluidity of the etching solution is not good, so the etching effect is difficult to control and cannot be removed reliably. The sacrificial layer around the microstructure 71 affects the performance of the microstructure 71, resulting in a decrease in process yield
[0008] Therefore, for the packaging method of the known microstructure, there is still room for improvement, both in the structure and in the process.

Method used

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Embodiment Construction

[0023] (common part)

[0024] Base 6 Microstructure 61

[0025] Cover 62 Notch 621

[0026] Space 63 Wafer 7

[0027] Microstructure 71 Covering 72

[0028] Hole 721 Space 73

[0029] encapsulation layer 74

[0030] (invention part)

[0031] Package Structure Process 1 Package Structure 1A, 1B

[0032] Substrate 11, 11B Through hole 111, 111B

[0033] Cover 12, 12B etch protection layer 112, 121

[0034] Etched areas 113, 122 Microstructure elements 13, 13B

[0035] Inner line 14, 14B Space 15, 15B

[0036] Bottom surface 151 Through holes 16, 16B

[0037] Packaging process 2 Packaging material 21

[0038] Ripening process 3 Ripening device 31

[0039] Cutting process 4 Vacuum coating device 5

[0040] Chamber 51 Vacuum pump 52

[0041] Rotary Platform 53 Motor 54

[0042] Encapsulating material spout 55 Encapsulating material conveying pipe 56

[0043] Control Platform 57

[0044] Please refer to FIG. 1 to FIG. 3 , which show the structure of the selec...

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Abstract

This is a method for wafer level vacuum encapsulation. Fix some tiny structure component on one base plate, and connect inner line of tiny structure component with bottom of base plate in type of inner line. Add one close cover on base plate and leave one space between close cover and each tiny structure component of base plate. Open at least one hole at each space position on the close cover for connecting the space and complete one encapsulation structure. Set it into one vacuum environment and achieve the vacuum state through all space and equably spread one layer of encapsulation stuff on close cover to fill each hole with encapsulation stuff and block out them, so the tiny structure components of each space all locate in vacuum state. The encapsulation stuff suffers over ripe and is incised into single encapsulation grain one by one.

Description

technical field [0001] The invention relates to a wafer-level vacuum packaging method, in particular to a method of coating packaging materials in a vacuum environment by means of wafer spin coating, and then cutting into individual packaging individuals. Background technique [0002] Traditional microstructures, such as optoelectronic elements, radio frequency elements and micro-electromechanical elements, etc., are packaged in the form of a single crystal grain when packaged, as shown in Figure 7, which is provided with a microstructure 61 on a base 6, and then A cover 62 is put on the base 6, and there is a space 63 in the cover 62 for accommodating the microstructure 61 on the base 6, and a gap 621 is provided on the side of the bottom end of the cover 62, The space 63 in the cover 62 is evacuated into a vacuum state, and then the gap 621 is sealed by dispensing to complete the package. [0003] Since the gap 621 of the cover 62 is opened on the side, the dispensing mus...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50
Inventor 邹庆福李鸿忠
Owner 邹庆福