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Memory module, memory system and method for controlling thereof

A technology of memory controller and memory system, applied in the field of memory system, can solve the problem that the performance of high-speed DRAM device cannot be utilized, etc.

Inactive Publication Date: 2007-04-25
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, the trunk link configuration cannot take advantage of the full performance of high-speed DRAM devices

Method used

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  • Memory module, memory system and method for controlling thereof
  • Memory module, memory system and method for controlling thereof
  • Memory module, memory system and method for controlling thereof

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0035] FIG. 3 is a block diagram illustrating a memory system according to an exemplary embodiment of the present invention.

[0036]Referring to FIG. 3 , the memory system includes a memory controller 100 and a memory module 200 . The memory controller 100 is connected to the memory module 200 through four bus channels CH0, CH1, CH2 and CH3. Each bus channel includes an n-bit download bus DLB and two m-bit upload buses PULB and SULB. An m-bit upload bus PULB is an upload bus for the main memory pack, and another m-bit upload bus SULB is an upload bus for the sub memory pack. The memory controller 100 provides a plurality of reference clock signals FCLK to the memory module 200 . Memory controller 100 includes some physically readable media, such as read only memory (ROM), static random access memory (SRAM), flash memory, etc., and includes program code to be written to and read from the media. For each channel, the memory module 200 includes a main memory component 210 and...

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Abstract

In a memory system and a memory module having a large capacity and operating at high speed, the memory module includes a module board, a primary memory component that is mounted on the module board, accessed as a master, and has a first column access latency, and a secondary memory component that is mounted on the module board, accessed as a slave, and has a second column access latency, which is shorter than the first column access latency. The memory system operates at high speed regardless of a repetition delay in a repeated link configuration in which the memory components are linked as hierarchy.

Description

[0001] Pursuant to 35 U.S.C §119, this application claims the benefit of Korean Patent Application No. 2005-97355 filed on October 17, 2005, the entire contents of which are hereby incorporated by reference. technical field [0002] The present application relates to a memory system and a method of controlling the memory system. More particularly, the present application relates to a memory system in which a main storage device and a secondary storage device are configured in a relay link configuration and a method of controlling the memory system. Background technique [0003] As the central processing units (CPUs) of computer systems become faster and more efficient, there is a need for faster and higher capacity synchronous dynamic random access memory (SDRAM). However, to date, SDRAM has lagged behind the speed of CPUs. Generally, the CPU receives and transfers data from / to SDRAM through the memory controller to buffer the data on the way. [0004] FIG. 1 is a block di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F12/00G11C11/4096
CPCG11C7/1066G11C5/04G11C2207/107G11C7/1045G11C7/22G06F12/08
Inventor 崔周善
Owner SAMSUNG ELECTRONICS CO LTD