A stacking type wafer packaging structure

Abstract

The static wafer package structure comprises: a substrate with a first wafer, multiple wires, a second wafer above the first one with multiple second pads on its active surface, and multiple B-stage conductive bumps. Wherein, these first welding pads are arranged on the active surface of the first wafer to connect with both substrate and the second pad; and bumps cover part wires.

Description

technical field [0001] The present invention relates to a chip package structure, and in particular to a stacked chip package structure. Background technique [0002] In today's highly informationized society, the market for multimedia applications continues to expand rapidly. Integrated circuit packaging technology also needs to cooperate with the digitalization, networking, regional connection and user-friendly development of electronic devices. In order to meet the above requirements, it is necessary to strengthen the requirements of high-speed processing, multi-functionality, accumulation, miniaturization, weight reduction and low price of electronic components. Therefore, different types of high-density packages have been developed, such as Ball grid arrays (BGA), Chip Scale Package (CSP), Flip Chip and stacked multi-chip packages. Packaging modules. [0003] FIG. 1 is a schematic cross-sectional view of a conventional stacked chip package structure. Referring to FI...

AI Technical Summary

Problems solved by technology

However, since the spacer 140 is disposed in the stacked chip package structure 100, its height cannot be reduced, and the requirement of compactness cannot be met.

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