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Method for parallelly detecting synchronous communication chips

A communication chip and chip technology, which is applied in the direction of electronic circuit testing, measuring electricity, measuring devices, etc., to achieve the effect of shortening test time, shortening test time and reducing test cost

Active Publication Date: 2007-06-13
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When it is necessary to use different test vectors for different DUTs, or write different data for each DUT, due to the design specifications of the existing tester and the limitations of the existing testing technology, it is impossible to simultaneously test multiple The chip is tested with different test vectors

Method used

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  • Method for parallelly detecting synchronous communication chips
  • Method for parallelly detecting synchronous communication chips
  • Method for parallelly detecting synchronous communication chips

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Embodiment Construction

[0011] The method for parallel testing of synchronous communication chips of the present invention first divides the different test vectors of all tested components into the memory of the tester according to the clock cycle, and then outputs all the stored data in parallel according to the clock cycle, thereby obtaining multiple tested components. Parallel testing of multiple test vectors for components, and simultaneous pass / failure judgments. Realize the simultaneous testing of different test vectors on multiple chips of the synchronous communication chip (see Figure 2).

[0012] The process of dividing and storing is: the first DUT coordinates of each simultaneous measurement are obtained through the probe station communication of the tester, and then according to the relative position of each DUT during the simultaneous measurement, the coordinate of each DUT can be calculated for each simultaneous measurement. The specific coordinates of a DUT. Then according to the specific ...

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Abstract

The invention discloses a method to take multi-chip parallel testing by using synchronous communication chip. It includes the following steps: taking division to the different test vectors according to time cycle, and restoring into memory of tester; outputting the data according to time cycle to gain paralleling testing and taking qualified / error judgment. The invention could improve testing efficiency of testing chip and lower testing time and cost.

Description

Technical field [0001] The invention relates to a test method for a large-scale integrated circuit synchronous communication chip, in particular to a method for realizing a multi-chip parallel test by a synchronous communication chip. Background technique [0002] For the existing test system, even if multiple synchronous communication chips can be tested simultaneously, the test vector used for each device under test (DUT, device under test) is completely the same (see Figure 1). When it is necessary to use different test vectors for different devices under test, or write different data for each device under test, due to the design specifications of the existing tester and the limitations of the existing test technology, it is impossible to simultaneously perform multiple tests. The chip is tested with different test vectors. Summary of the invention [0003] The technical problem to be solved by the present invention is to provide a method for parallel testing of synchronous c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3183
Inventor 武建宏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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