Internal power-source potential supply circuit, step-up potential generating system, output potential supply circuit, and semiconductor memory

Abstract

An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

Description

[0001] 1. Field of the Invention[0002] The present invention relates to an internal power-source potential supply circuit for supplying an internal power-source potential to a predetermined load.[0003] 2. Description of the Background Art[0004] FIG. 98 is a circuit diagram of a conventional internal power-source potential supply circuit for use in a semiconductor device. As shown, an external power-source potential VCE is applied as an internal power-source potential VCI to a load 11 through a PMOS transistor Q1. A comparator 1 has a negative input receiving a reference potential Vref and a positive input receiving the internal power-source potential VCI as a feedback signal, and provides a control signal S1 based on the result of comparison between the reference potential Vref and the internal power-source potential VCI to the gate of the PMOS transistor Q1.[0005] In such an arrangement, if the internal power-source potential VCI is lower than the reference potential Vref, the cont...

AI Technical Summary

Benefits of technology

This solution effectively stabilizes the internal power-source potential, reducing current consumption and operation delays, and improves the retention characteristics of semiconductor memory cells by varying the cell plate potential and precharge potential.

Problems solved by technology

In the arrangement of FIG. 98, a small difference between the external power-source potential VCE and the internal power-source potential VCI deteriorates the characteristics of the comparator 1, resulting in a delay in operation and a large amount of temporary reduction in internal power-source potential VCI.

The internal power-source potential VCI grows higher than required, resulting in dangers of an increase in current consumption and a lower degree of reliability.

In this manner, the conventional internal power-source potential supply circuits are disadvantageous in that variations in the external power-source potential may cause decreased performance of the circuit, finding difficulties in supplying the internal power-source potential with high accuracy.

This decreases the performance of the transistor of the internal circuit to generally lower the circuit operation speeds.

Such is the case in testing a DRAM for memory cell retention characteristics wherein it is desired to make the substrate potential deeper than usual so that the retention characteristics are prone to deteriorate to shorten the test time.

For example, the chip may consume a large amount of current to temporarily drop the internal power-source potential VCI.

For example, the chip may consume a large amount of current to temporarily drop the internal power-source potential VCI, influencing the operation of the internal circuit within the load 11 receiving the temporarily dropped internal power-source potential VCI.

However, the output from the comparator 1 does not fully swing to "L" but varies in an analog fashion.

The comparator 1 is so sensitive that a slight change in layout places the comparator 1 into an unbalanced condition.

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