PLL circuit

Abstract

Disclosed is a PLL circuit that makes fractional frequency division possible without causing spurious components to be produced in the output of a VCO. The PLL circuit comprises a frequency dividing circuit for frequency-dividing the output of a VCO; a phase adjusting circuit, to which are input two clocks of different phases obtained by frequency division performed by the frequency dividing circuit, for producing an output signal having a delay time defined by a time that is the result of internally dividing a timing difference between the two clocks; a charge pump for generating a voltage conforming to a phase difference output from the phase comparator circuit; and a loop filter for smoothing the voltage conforming to the phase difference and applying the voltage to the VCO, wherein the dividing value of the timing difference in the phase adjusting circuit is represented by MF / MD, and an accumulation operation is performed in units of MF every frequency-divided clock. If the cumulative result by MF is equal to or greater than MD, then a remainder obtained by dividing the cumulative result by MD is adopted as the cumulative result and the dividing ratio of the frequency dividing circuit is set to N+1. A control signal for setting the dividing ratio of the timing difference in the phase adjusting circuit is output to the phase adjusting circuit, and a clock obtained by frequency-dividing the output of the VCO in accordance with a dividing ratio N+MF / MD is input to a phase comparator.

Description

[0001] This invention relates to a phase-locked loop circuit and, more particularly, to a phase-locked loop circuit of fractional frequency-dividing type.BACKGROUND OF THE INVENITON[0002] In order to control the frequency of an output signal at a frequency interval smaller than the frequency of a reference signal, the conventional practice is to employ an arrangement which averages, in terms of time, a frequency dividing ratio of a programmable frequency dividing circuit with the frequency dividing ratio being variable in an ordinary phase-locked loop (PLL) to implement a frequency dividing ratio of an accuracy finer than a decimal-point by using the average value. A configuration in which the dividing ratio of a frequency dividing circuit is changed and averaged in terms of time to implement fractional frequency division in equivalent terms is also referred to as a fractional frequency-dividing system.[0003] If one period 1 / fr of a reference signal of which frequency is fr is adopt...

AI Technical Summary

Benefits of technology

[0017] Accordingly, it is an object of the present invention to provide an entirely novel PLL circuit that makes fractional frequency division possible without causing spurious signals to be produced in the output of a voltage-controlled oscillator.

Problems solved by technology

As a consequence, a problem with the prior art is that the circuitry for reducing spurious signals becomes large in scale.

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