Systems and methods for batched USB data transfers

Abstract

A USB host controller for embedded systems employing batched data transfer. The system batches up to 16 individual transactions in a single batch to reduce the number and frequency of interrupts to the microprocessor and to increase USB data throughput.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of electronic devices and the transfer of data there between and, in particular, to providing a host controller and host controller driver interface to microprocessor based embedded systems for interconnecting devices via a serial bus. More specifically, the present invention relates to a Universal Serial Bus (USB) host controller and host controller driver interface for embedded systems that employ batched data transfer. 2. Description of the Related Art Electronic devices are often electrically connected to one or more other electronic devices. For example, microprocessor based systems, such as personal computers, are often connected to one or more peripheral devices such as printers, scanners, graphics tablets, digital cameras and the like. The connection to peripheral devices can take place via a number of known serial or parallel interfaces. The Universal Serial Bus (USB) is on...

AI Technical Summary

Benefits of technology

The aforementioned needs are satisfied by the present invention which in one aspect comprises a USB host controller system for interfacing between at least one USB device and a host processor. The system comprises a host controller that transfers USB transactions between at least one USB device and a host processor. The system further includes at least one memory associated with the host controller, wherein the host controller stores the information indicative of a plurality of USB transactions in the memory and executes a plurality of stored USB transactions in a single batch so as to reduce the overall resource demands on the host processor to execute the USB transactions and to increase data throughput on the USB.

In another aspect, the invention comprises a method of interfacing a plurality of USB device with a host processor. The method comprises assembling a first batch of USB transactions in a memory, sequentially executing each of the USB transactions of the first batch in the memory and sending an interrupt signal to a host processor indicating that the first batch of transactions has been completed so that the host processor is interrupted less thereby reducing the overall resource demand on the host processor during execution of the first batch.

In yet another aspect, the invention comprises a USB host controller that is adapted to receive and assemble information indicative of a plurality of USB transactions from a host processor wherein the USB host controller executes an assembled batch of a plurality of USB transactions upon meeting a certain condition and wherein the host processor is informed of the availability of the status of the plurality of transactions upon completion of the batch to thereby reduce the overall resource demand on the host processor during execution of the batch of USB transactions.

Problems solved by technology

However, there is a need for a USB Host Controller for embedded systems and microprocessors which do not have a bus interface with bus mastering capability such as a PCI bus.

In the prior art, these embedded Host Controllers suffer the shortcoming of low data transfer rate and frequent interrupts to the microprocessor because the microprocessor is interrupted every transaction.

Moreover, each interrupt of the microprocessor involves an interrupt latency period.

The interrupt latency period and the interrupt recovery period waste the microprocessor's time.

That is, there is no data on the USB bus, which results in very low data throughput.

The process also slows the microprocessor system as the microprocessor must cease operating on whatever task before the interrupt, attends to the USB host controller, and then recover its working environment to pick up again where it was before.

The time to cease operation, store the registers and context, and then later retrieve the registers and context and resume processing contributes greatly to the increased inefficiency of the microprocessor during USB interrupts.

This can significantly reduce the throughput of the USB connection, as well as the performance of the microprocessor system, below optimum.

While this method does significantly improve the throughput of the USB, it is not applicable to many embedded systems where there is no reverse bus mastering mechanism either due to cost reasons, architectural or software considerations.

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