Strained silicon on relaxed sige film with uniform misfit dislocation density

Abstract

A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

Description

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION [0001] The invention relates to methods for manufacturing semiconductor devices having improved device performances, and, more particularly to methods for forming a relaxed SiGe film. BACKGROUND DESCRIPTION [0002] The escalating requirements for ultra large scale integration semiconductor devices require ever increasing high performance and density of transistors. With device scaling-down reaching limits, the trend has been to seek new materials and methods that enhance device performance. One of the most direct methods to increase performance is through mobility enhancement. It has been known that stress or strain applied to semiconductor lattice structures can improve device performances. For example, an N type device formed on an biaxially strained (e.g., an expanded lattice) silicon substrate exhibits better device performances than other N type devices formed on a silicon substrate without strain (or the expanded lattice struct...

AI Technical Summary

Benefits of technology

The invention provides methods for manufacturing semiconductor devices by forming a compressively strained SiGe layer on a silicon substrate and then controllably ion-implanting atoms into the SiGe layer to create uniformly distributed interstitial dislocation loops. These loops nucleate misfit dislocations in the SiGe layer, which can then be annealed to form a relaxed SiGe layer on the substrate. This method results in a semiconductor device with improved performance and stability.

Problems solved by technology

However, the problem with this conventional approach is that it requires a multi-layered SiGe buffer layer that is very thick (e.g., a thickness of approximately 5000 Å to 15000 Å) to achieve misfit dislocations on its surface portion while avoiding threading dislocations between the SiGe layer and the silicon substrate layer, thereby achieving a relaxed SiGe structure on the surface of the multi-layered SiGe layer.

Also, this approach significantly increases manufacturing time and costs.

Further, the thick graded SiGe buffer layer cannot be easily applicable to silicon-on-substrate (SOI).

The SiGe buffered layer structure is too thick.

Another problem is that misfit dislocations formed between the SiGe layer and the silicon epitaxial layer are random and highly non-uniform and cannot be easily controlled due to heterogeneous nucleation that cannot be easily controlled.

Also, misfit dislocation densities are significantly different from one place to another.

Thus, the physical stress derived from the non-uniform misfit dislocations are apt to be also highly non-uniform in the silicon epitaxial layer, and this non-uniform stress causes non-uniform benefits for performance with larger variability.

Further at those locations where misfit density are high, the defects degrade device performances through shorting device terminals and through other significant leakage mechanisms.

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