System resource router

Abstract

A system resource router for SOC applications is described. Data-transfer initiators coupled to the router via one of a plurality of channel socket connections (144, 146, 148, 150, 152, 154) alternatively couple to internal M-channel buses (162, 164, 166) using transfer switches (168, 170, 172). Each internal M-channel bus connects to an external M-channel bus (114, 116, 118) populated by one or more transaction targets using an M-channel controller (156, 158, 160). The channel sockets, at least some of the data-transfer initiators, the internal M-channel buses, the external M-channel buses, and at least some of the transaction targets are all contained upon a single integrated circuit (IC) SOC device. Split reads and full duplex transactions are supported. Transactions can occur at different clock frequencies and bandwidths.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. Pat. No. 6,769,046, filed 5 Dec. 2000 (5 Dec. 2000), which is also a continuation in part of U.S. Pat. No. 6,601,126, filed 2 May 2000 (2 May 2000). Additionally, the prior U.S. Pat. No. 6,769,046 claims the benefits of the earlier filed U.S. Provisional Application No. 60 / 182,406 and U.S. Provisional Application No. 60 / 217,597. All of these documents are incorporated by reference for all purposes into this specification.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to electronic circuits, and more specifically to functional modules on a single semiconductor integrated circuit. [0004] 2. Description of the Related Art [0005] The semiconductor art has advanced to the point where whole systems are preferably integrated onto a single-chip device. Processing speeds and architectures are such that very wide buses operated at near gigahert...

AI Technical Summary

Benefits of technology

[0016] An advantage of the present invention is that a system resource router is provided that divides a high-speed bus into M-channel sub-busses and uses switches at initiator sockets to connect to the different M-channels.

[0017] Another advantage of the present invention is that dividing a single, high bus into multiple M-channel sub buses enables local routing of each M-channel sub bus and eliminates unnecessary connections.

[0018] Another advantage of the present invention is that a system resource router is provided that allows different initiator-to-target or memory transactions to occur simultaneously across different M-channels.

[0019] A further advantage of the present invention is that a system resource router is provided that increases the bandwidth of the system without resorting to larger bus widths or higher clock frequencies.

[0020] These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the drawings.

Problems solved by technology

Off chip, such a bus switch architecture would be impractical.

A disadvantage is that all data passes over the same wires and there is no parallelism.

But even these increases have limitations, because in a typical system, most transfers are not a full data path wide.

But this variation still has the same routing problem, because each initiator can still talk to each target across the bridge.

This means the bus still routes across the chip and will have problems at high clock frequencies.

The bridge also adds two levels of logic to the data, address, and control signals making it the limiting factor for performance.

The point-to-point architecture is an architecture that can only be used to its fullest in on-chip designs due to package-pin limitations.

A disadvantage of the point-to-point architecture is the number of accessible target devices is limited.

As more and more targets are added, the switching network becomes more difficult to implement.

Changes to the switching network in the middle of the design become practically impossible.

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