FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections

a technology of integrated circuits and memory blocks, applied in the field of integrated circuits, can solve the problems of limiting the ability of a given fpga architecture to implement certain speed-critical designs, unable to complete its mission successfully on a first try, and modern fpga's tend to be fairly complex, so as to maximize the data output (data reading) bandwidth of embedded memory, increase the overall system bandwidth, and maximize bandwidth

a technology of integrated circuits and memory blocks, applied in the field of integrated circuits, can solve the problems of limiting the ability of a given fpga architecture to implement certain speed-critical designs, unable to complete its mission successfully on a first try, and modern fpga's tend to be fairly complex, so as to maximize the data output (data reading) bandwidth of embedded memory, increase the overall system bandwidth, and maximize bandwidth

USRE39510E1Inactive Publication Date: 2007-03-13LATTICE SEMICON CORP
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  • FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections
  • FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections
  • FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections

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Experimental program
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Embodiment Construction

[0075]FIG. 1 shows a macroscopic view of an FPGA device 100 in accordance with the invention. The illustrated structure is preferably formed as a monolithic integrated circuit.

[0076]The macroscopic view of FIG. 1 is to be understood as being taken at a magnification level that is lower than later-provided, microscopic views. The more microscopic views may reveal greater levels of detail which may not be seen in more macroscopic views. And in counter to that, the more macroscopic views may reveal gross architectural features which may not be seen in more microscopic views. It is to be understood that for each more macroscopic view, there can be many alternate microscopic views and that the illustration herein of a sample microscopic view does not limit the possible embodiments of the macroscopically viewed entity. Similarly, the illustration herein of a sample macroscopic view does not limit the possible embodiments into which a microscopically viewed embodiment might be included.

[00...

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Abstract

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The following copending U.S. patent applications are owned by the owner of the present application, and their disclosures are incorporated herein by reference:[0002](A) Ser. No. 08 / 948,306 filed Oct. 9, 1997 by Om P. Agrawal et al. and originally entitled, “VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS”;[0003](B) (A) Ser. No. 08 / 996,049 filed Dec. 22, 1997 by Om P. Agrawal et al and originally entitled, DUAL PORT SRAM MEMORY FOR RUN-TIME USE IN FPGA INTEGRATED CIRCUITS;[0004](C) Ser. No. 08 / 996,361 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “SYMMETRICAL, EXTENDED AND FAST DIRECT CONNECTIONS BETWEEN VARIABLE GRAIN BLOCKS IN FPGA INTEGRATED CIRCUITS”;[0005](D) Ser. No. 08 / 995,615 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “A PROGRAMMABLE INPUT / OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS”;[0006](E) Ser. No. 08 / 995,614 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitl...

Claims

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Application Information

Patent Timeline
13 Mar 2007
Publication
USRE39510E1
IPC
G06F7/38; H03K19/177
CPC
H03K19/17728; H03K19/17736; H03K19/17748; H03K19/1776
Inventors
AGRAWAL, OM P.; CHANG, HERMAN M.