Fabrication method of semiconductor integrated circuit device

Abstract

Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application claims priority from Japanese patent application No. 2003-372323, filed on Oct. 31, 2003, the content of which is hereby incorporated by reference into this application. BACKGROUND OF THE INVENTION [0002] The present invention relates to a technique for use in the fabrication of semiconductor integrated circuit devices, and, more particularly, to a technique that can be effectively applied to electrical inspection of semiconductor integrated circuits in a semiconductor wafer state. [0003] For instance, there is a known technique for use in forming contact terminals, lead-out wiring and the like of an inspection apparatus for use in probing semiconductor integrated circuits in a wafer state (see Patent Reference 1 and Patent Reference 2, for example). By this method, a mold for shaping contact terminals is prepared by anisotropic etching of a silicon wafer, for example, and contact terminals, lead-out wiring and th...

AI Technical Summary

Benefits of technology

[0015] In recent years, probing of semiconductor integrated circuit devices has involved the use of techniques applicable to a semiconductor wafer (hereinafter to be simply referred to as a wafer) state to meet requirements for compatibility with shipment in a wafer form (for qualitative differentiation), compatibility with a Known Good Die (KGD) (for raising the yield of multi-chip package (MCP)) and reductions in total cost.

[0035] In the electrical inspection of semiconductor integrated circuit devices, damage to test pads, inter-layer insulating films, semiconductor elements and wiring can be reduced.

Problems solved by technology

The wiping of the probes not only breaks the natural oxide film over the surface of the test pads, but also damages the surface of the test pads themselves.

This results in a problem in that the adhesion of the bonding wires connected to those test pads becomes weaker in the rest of the fabrication process.

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