Circuit for modifying a clock signal to achieve a predetermined duty cycle

Abstract

The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator (102) configured in a feedback loop, the output of the charge pump integrator (102) operable as a controlling node to delay inverter (115). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator (102) will, through PBIAS, cause delay inverter 115 to delay of the rising edge of CLKIN through delay inverter (115). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.

Description

RELATED APPLICATIONS [0001] This application is related to U.S. Provisional patent application Attorney Docket #TI-35201, entitled Variable Adaptive Quantization in Sigma-Delta Modulators, filed Feb. 13, 2003, Ser. No. 60 / 477,160 and U.S. Patent applications Attorney Docket # TI-35202 entitled Improved Level-Shifter each filed herewith, the teachings of each application incorporated herein by reference.FIELD OF THE INVENTION [0002] The present invention generally relates to circuits designed to output timing and clock signals with a desired duty cycle. BACKGROUND OF THE INVENTION [0003] The duty cycle is an important characteristic of a periodic digital waveform. The duty cycle is generally defined as the ratio of the pulse width (tw) to the period (T) and can be expressed as a percentage. Duty⁢ ⁢cycle=(twT)⁢100⁢%[0004] The demand for less expensive, lower power and yet more reliable integrated circuit components for use in communication, imaging and high-quality video applications...

AI Technical Summary

Benefits of technology

"The present invention is a circuit designed to modify a clock signal with a different frequency and duty cycle than what is needed for a subsequent stage or circuit of a device. The circuit achieves this by using a charge pump integrator with a certain ratio of current sources to achieve a desired duty cycle. This negative feedback loop adjusts the delay in the circuit to achieve the desired duty cycle. The circuit can use only 2 to 3 micro-amps of power supply current and can be used in devices requiring a clock signal with a 50% duty cycle."

Problems solved by technology

This is problematic as DSPs are sensitive to the duty cycle of the clock signal.

However, it is well known in the art that increasing the clock frequency increases the power consumption of a circuit.

However, these circuits are complex, requiring many more semiconductor devices, and thus increased chip surface area.

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