Trench corner effect bidirectional flash memory cell

Abstract

A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the oxide-filled trench. Source / drain regions are adjacent the trench sides with the trapping material. An energy barrier between the drain and source regions has two local high points that correspond to the trench corners. To read the device, sufficient gate voltage is applied to invert the channel and a sufficient drain voltage is applied to pull down the drain-side barrier. If charges of opposite polarity are trapped in the source-side trench corner, the source barrier will be significantly lowered so that current flows between source and drain under read conditions.

Description

RELATED APPLICATION [0001] This Application is a Divisional of U.S. application Ser. No. 10 / 656,636, titled “TRENCH CORNER EFFECT BIDIRECTIONAL FLASH MEMORY CELL,” filed Sep. 5, 2003, (allowed) which is commonly assigned and incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to memory cells and in particular the present invention relates to structures of non-volatile memory cells. BACKGROUND OF THE INVENTION [0003] In order for memory manufacturers to remain competitive, memory designers must constantly increase the density of flash memory devices. Increasing the density of a flash memory device generally requires reducing spacing between memory cells. It is becoming increasingly difficult to further reduce spacing between memory cells. Closer packing also generally requires smaller dimensions of device elements. [0004] Smaller dimensions of many device elements may cause operational problems with the cell. For example, t...

AI Technical Summary

Benefits of technology

This design enables compact, high-density memory cells with improved operational reliability by isolating charge trapping layers and controlling energy barriers, enabling efficient programming and erasing while preventing unwanted charge migration.

Problems solved by technology

It is becoming increasingly difficult to further reduce spacing between memory cells.

Smaller dimensions of many device elements may cause operational problems with the cell.

For example, the channel between the source / drain regions becomes shorter possibly causing severe short channel effects.

Additionally, smaller size cells with a continuous layer of oxide-nitride-oxide (ONO) may have a problem with charge migrating from one bit-storage point to the other.

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