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Semiconductor devices having self-aligned bodies and methods of forming the same

a technology of self-aligning bodies and semiconductor devices, which is applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of reducing the performance of the device, reducing the stand-by current, and so on

Inactive Publication Date: 2006-06-01
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0031] Some embodiments of the invention are directed to a structure having self-aligned body and gate regions. Self alignment of the body and gate regions may reduce the possibility of the formation of a short circuit between the body region and the source and / or drain region. Some embodiments of the invention are directed to methods of forming such devices.

Problems solved by technology

As channel lengths of MOS (metal-oxide-semiconductor) transistor devices decrease, certain secondary effects, known as short channel effects, may decrease the performance of the devices.
However, one drawback of SOI devices may be the accumulation of electrical charges in the body of the device.
Since the electric potential of the body rises only when the device is turned on, the threshold voltage may drop, thereby reducing the stand-by current while shortening the device access time.
Unfortunately, the process used to manufacture such a device may be complex.
Additionally, if the body region 34 and the gate pattern 38a are misaligned, the body region 34 may be exposed, which may result in the formation of an unwanted short circuit between the source and / or drain of the device and the body region 34.

Method used

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  • Semiconductor devices having self-aligned bodies and methods of forming the same
  • Semiconductor devices having self-aligned bodies and methods of forming the same
  • Semiconductor devices having self-aligned bodies and methods of forming the same

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Embodiment Construction

[0059] The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer or intervening elements or layers may be present.

[0060] Like reference numerals refer to like elements throughout. As used herein the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0061...

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PUM

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Abstract

A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

Description

CLAIM OF PRIORITY AND CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims priority to Korean Patent Application No. 2004-76797, filed on Sep. 24, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor devices, and, more particularly, to semiconductor devices having a body contact and methods of forming the same. BACKGROUND [0003] As channel lengths of MOS (metal-oxide-semiconductor) transistor devices decrease, certain secondary effects, known as short channel effects, may decrease the performance of the devices. In a MOS transistor formed on an SOI (silicon on insulator) substrate, short channel effects may be suppressed due to full or partial depletion of the channel region. However, one drawback of SOI devices may be the accumulation of electrical charges in the body of the device. Such charge accumulation may increa...

Claims

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Application Information

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IPC IPC(8): H01L27/12
CPCH01L21/84H01L27/1203H01L29/66772H01L29/783H01L29/78606H01L29/78654H01L21/18H01L21/28
Inventor JEONG, JAE-HUNLIM, HOONJUNG, SOON-MOONCHO, HOO-SUNG
Owner SAMSUNG ELECTRONICS CO LTD