Field effect transistor with metal source/drain regions

Abstract

A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source / drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of semiconductor devices and more particularly to a semiconductor device having a source / drain region comprising a semiconductor portion and a metal portion. [0003] 2. Discussion of Related Art [0004] In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of an ideal subthreshold gradient for optimized on-current / off-current ratios. An example of an proposed SOI transistor which can be operated in a fully depleted manner is a tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on insulating substrate 102 having a buried oxide layer 103 formed on a monocrystalli...

AI Technical Summary

Problems solved by technology

Unfortunately, as tri-gate devices become increasingly smaller, the external contact resistance (Rext) is increasingly becoming more significant portion of the overall device resistance.

Unfortunately, standard techniques for reducing contact resistance, such as by forming “raised” source / drain regions where additional epitaxial silicon is formed on the silicon body 104 is difficult to implement in nonplanar transistors.

For example, it is difficult to grow “raised” epitaxial source / drain regions on the sides of the silicon body 104.

For these reasons the devices suffer from high Rext and degraded performance.

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