Display

Abstract

A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a display, and more particularly, it relates to a display comprising a shift register circuit. [0003] 2. Cross-Reference to Related Applications [0004] The priority application number JP2005-96631 upon which this patent application is based is hereby incorporated by reference. [0005] 3. Description of the Background Art [0006] A display comprising a shift register circuit is known in general, as disclosed in Japanese Patent Laying-Open No. 2005-17973, for example. [0007]FIG. 18 is a circuit diagram for illustrating the circuit structure of a shift register circuit driving drain lines of the exemplary conventional display disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-17973. Referring to FIG. 18, the shift register circuit driving the drain lines of the exemplary conventional display is provided with a plurality of stages of shift register circuit portions 1001 t...

AI Technical Summary

Benefits of technology

[0019] In the display according to the aforementioned aspect, both of the first shift register circuit portion and the second shift register circuit portion preferably include the reset transistors. According to this structure, the display can fix both of the first and second shift signals output from the first and second shift register circuit portions respectively to the second voltage supply source not turning on the transistors of the logic composition circuit portion with the reset transistors. Thus, the display can hold both of two transistors of the logic composition circuit portion in OFF-states when inputting the first and second shift signals in the gates of the two transistors of the logic composition circuit portion respectively and employing a signal output through the two transistors as the shift output signal obtained by logically compositing the first and second shift signals with each other. Therefore, the display can more reliably inhibit the logic composition circuit portion from outputting a signal to the gate line or the drain line at unintentional timing.

[0034] In the display according to the aforementioned aspect, transistors constituting the first shift register circuit portion and the second shift register circuit portion and the transistors constituting the logic composition circuit portion as well as the reset transistor are preferably of a first conductive type. According to this structure, the numbers of ion implantation steps and ion implantation masks for forming these transistors can be reduced as compared with a case of forming the transistors constituting the first shift register circuit portion, the second shift register circuit portion and the logic composition circuit portion and the reset transistor by transistors having two conductive types, i.e., first and second conductive types. Thus, complication of a manufacturing process as well as the manufacturing cost can be suppressed.

Problems solved by technology

Thus, the transistors NT510 to NT512 of the horizontal switch 1100 having the gates connected to the nodes ND504 may disadvantageously enter ON-states at unintentional timing.

In this case, the shift register circuit disadvantageously outputs the video signals from the video signal line Video to the drain lines through the ON-state transistors NT510 to NT512 at unintentional timing.

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