Display

Abstract

A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a display, and more particularly, it relates to a display comprising a shift register circuit. [0003] 2. Cross-Reference to Related Applications [0004] The priority application number JP2005-96631 upon which this patent application is based is hereby incorporated by reference. [0005] 3. Description of the Background Art [0006] A display comprising a shift register circuit is known in general, as disclosed in Japanese Patent Laying-Open No. 2005-17973, for example. [0007]FIG. 18 is a circuit diagram for illustrating the circuit structure of a shift register circuit driving drain lines of the exemplary conventional display disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-17973. Referring to FIG. 18, the shift register circuit driving the drain lines of the exemplary conventional display is provided with a plurality of stages of shift register circuit portions 1001 t...

AI Technical Summary

Benefits of technology

[0030] In the aforementioned structure including the fourth and fifth transistors, the display preferably connects the first signal line supplying the first signal switched between the first voltage supply source and the second voltage supply source to the drain of the fourth transistor and supplies a first clock signal to the gate of the fourth transistor, connects the first signal line supplying the first signal to the drain of the fifth transistor and supplies a second clock signal to the gate of the fifth transistor, and switches the first signal from the second voltage supply source to the first voltage supply source after changing the first clock signal from the second voltage supply source to the first voltage supply source and after changing the second clock signal from the second voltage supply source to the first voltage supply source respectively. According to this structure, the display can change the source voltage supply source of the fourth transistor (fifth transistor) from the second voltage supply source to the first voltage supply source with the first signal after turning on the fourth transistor (fifth transistor) following the operation of changing the gate voltage supply source of the fourth transistor (fifth transistor) from the second voltage supply source to the first voltage supply source with the first clock signal (second clock signal). Thus, the display can raise or lower the gate voltage supply source of the fourth transistor (fifth transistor) along with the current change of the source voltage supply source of the fourth transistor (fifth transistor). In other words, the display can further raise or lower the gate voltage supply source of the fourth transistor (fifth transistor) along with the change of the source voltage supply source from the second voltage supply source to the first voltage supply source in addition to rise or fall of the gate voltage supply source of the fourth transistor (fifth transistor) caused by the first capacitor (second capacitor) provided between the gate and the source of the fourth transistor (fifth transistor) when supplying the fixed first voltage supply source to the drain of the fourth transistor (fifth transistor). Thus, the display can more easily set the voltage supply sources of the first and second shift signals to the level higher than VDD by at least the threshold voltage (Vt) or the level lower than VBB by at least the threshold voltage (Vt). Therefore, the display, capable of more easily supplying the first and second shift signals having the voltage supply source of at least VDD+Vt or not more than VBB−Vt to the gates of the second and third transistors of the logic composition circuit portion, can further inhibit the voltage supply source of the shift output signal output through the second and third transistors from going down or going up by the threshold voltage (Vt).

[0031] In the aforementioned structure including the fourth and fifth transistors, the display preferably connects a second signal line supplying a second signal switched between the first voltage supply source and the second voltage supply source to the drain of the fourth transistor and supplies a first clock signal to the gate of the fourth transistor, connects a third signal line supplying a third signal switched between the first voltage supply source and the second voltage supply source to the drain of the fifth transistor and supplies a second clock signal to the gate of the fifth transistor, switches the second signal from the second voltage supply source to the first voltage supply source after changing the first clock signal from the second voltage supply source to the first voltage supply source, and switches the third signal from the second voltage supply source to the first voltage supply source after changing the second clock signal from the second voltage supply source to the first voltage supply source. According to this structure, the display can change the source voltage supply sources of the fourth and fifth transistors from the second voltage supply source to the first voltage supply source at the timing for turning on the fourth transistor of the first shift register circuit portion and the fifth transistor of the second shift register circuit portion in response to the first and second clock signals respectively. Further, the display can hold the source voltage supply sources of the fourth and fifth transistors at the first voltage supply source respectively until the fourth transistor of the first shift register circuit portion and the fifth transistor of the second shift register circuit portion enter OFF-states in response to the first and second clock signals respectively. Thus, the display can suppress occurrence of such inconvenience that the gate voltage supply sources of the fourth and fifth transistors fluctuate due to change of the source voltage supply sources of the fourth and fifth transistors to the second voltage supply source before the fourth and fifth transistors enter OFF-states in response to the first and second clock signals respectively. In this case, the display, capable of suppressing fluctuation of the first and second shift signals output from the nodes connected with the gates of the fourth transistor of the first shift register circuit portion and the fifth transistor of the second shift register circuit portion respectively, can suppress destabilization of operations of the second and third transistors of the logic composition circuit portion receiving the first and second shift signals in the gates thereof respectively.

[0032] In the aforementioned structure including the fourth and fifth transistors, the reset transistor preferably also has a function of resetting the voltage supply source of the source of the fourth transistor or the fifth transistor to the second voltage supply source in response to the output signal from the shift register circuit portion precedent thereto by at least two stages with respect to the scanning direction. According to this structure, the display can reliably raise the gate voltage supply source of the fourth transistor (fifth transistor) by voltage supply source difference in the voltage supply source of the source of the fourth transistor (fifth transistor) going up from the lower voltage supply source VBB to the higher voltage supply source VDD by resetting the voltage supply source of the source of the fourth transistor (fifth transistor) to the lower voltage supply source VBB (second voltage supply source) in response to the output signal from the shift register circuit portion precedent thereto by at least two stages with respect to the scanning direction before raising the voltage supply source of the source of the fourth transistor (fifth transistor) by supplying the higher voltage supply source VDD (first voltage supply source) to the drain of the fourth transistor (fifth transistor) formed by an n-channel transistor, for example. Thus, the display, capable of further raising the gate voltage supply source of the fourth transistor (fifth transistor) as compared with a case of raising the voltage supply source of the source of the fourth transistor (fifth transistor) from an instable level between the higher and lower voltage supply sources VDD and VBB, can more reliably raise the gate voltage supply source of the fourth transistor (fifth transistor) to the level higher than VDD by the prescribed voltage (Vα) of at least the threshold voltage (Vt) of the fourth transistor (fifth transistor). Further, the display can lower the gate voltage supply source of the fourth transistor (fifth transistor) by voltage supply source difference in the voltage supply source of the source of the fourth transistor (fifth transistor) going down from the higher voltage supply source VDD to the lower voltage supply source VBB by resetting the voltage supply source of the source of the fourth transistor (fifth transistor) to the higher voltage supply source VDD (second voltage supply source) in response to the output signal from the shift register circuit portion precedent thereto by at least two stages with respect to the scanning direction before lowering the voltage supply source of the source of the fourth transistor (fifth transistor) by supplying the lower voltage supply source VBB (first voltage supply source) to the drain of the fourth transistor (fifth transistor) formed by a p-channel transistor. Thus, the display, capable of further lowering the gate voltage supply source of the fourth transistor (fifth transistor) as compared with a case of lowering the voltage supply source of the source of the fourth transistor (fifth transistor) from an instable level between the higher and lower voltage supply sources VDD and VBB, can more reliably lower the gate voltage supply source of the fourth transistor (fifth transistor) to the level lower than VBB by the prescribed voltage (Vα) of at least the threshold voltage (Vt) of the fourth transistor (fifth transistor).

[0033] The display according to the aforementioned aspect preferably applies the shift register circuit to at least either a shift register circuit for driving a gate line or a shift register circuit for driving a drain line. According to this structure, the display can easily inhibit the shift register circuit from outputting a signal to at least either the gate line or the drain line at unintentional timing.

[0034] In the display according to the aforementioned aspect, transistors constituting the first shift register circuit portion and the second shift register circuit portion and the transistors constituting the logic composition circuit portion as well as the reset transistor are preferably of a first conductive type. According to this structure, the numbers of ion implantation steps and ion implantation masks for forming these transistors can be reduced as compared with a case of forming the transistors constituting the first shift register circuit portion, the second shift register circuit portion and the logic composition circuit portion and the reset transistor by transistors having two conductive types, i.e., first and second conductive types. Thus, complication of a manufacturing process as well as the manufacturing cost can be suppressed.

Problems solved by technology

Thus, the transistors NT510 to NT512 of the horizontal switch 1100 having the gates connected to the nodes ND504 may disadvantageously enter ON-states at unintentional timing.

In this case, the shift register circuit disadvantageously outputs the video signals from the video signal line Video to the drain lines through the ON-state transistors NT510 to NT512 at unintentional timing.

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